Revision history
About this document
Product overview
Block diagram
Peripheral interface
Application core
CPU
Memory
VMC — Volatile memory controller
NVMC — Non-volatile memory controller
FICR — Factory information configuration registers
UICR — User information configuration registers
EasyDMA
AHB multilayer interconnect
Power and clock management
Power management
Power supply
Power supply monitoring
Clock management
Reset
Current consumption
POWER — Power control
CLOCK — Clock control
REGULATORS — Voltage regulators control
Peripherals
CRYPTOCELL — Arm TrustZone CryptoCell 310
DPPI - Distributed programmable peripheral interconnect
EGU — Event generator unit
GPIO — General purpose input/output
GPIOTE — GPIO tasks and events
IPC — Interprocessor communication
I2S — Inter-IC sound interface
KMU — Key management unit
PDM — Pulse density modulation interface
PWM — Pulse width modulation
RTC — Real-time counter
SAADC — Successive approximation analog-to-digital converter
SPIM — Serial peripheral interface master with EasyDMA
SPIS — Serial peripheral interface slave with EasyDMA
SPU — System protection unit
TIMER — Timer/counter
TWIM — I2C compatible two-wire interface master with EasyDMA
TWIS — I2C compatible two-wire interface slave with EasyDMA
UARTE — Universal asynchronous receiver/transmitter with EasyDMA
WDT — Watchdog timer
LTE modem
Non-Terrestrial Network
SIM card interface
LTE coexistence interface
LTE RF control external interface
RF front-end interface
Electrical specification
DECT NR+
GPS receiver
Debug and trace
Trace
CTRL-AP - Control access port
TAD - Trace and debug control
Hardware and layout
Pin assignments
Mechanical specifications
Reference circuitry
Reflow conditions
Shelf and floor life
Assembly-related instructions
Operating conditions
Absolute maximum ratings
Ordering information
Regulatory information
Legal notices

Block diagram

The block diagram illustrates the overall system. Arrows with white heads indicate signals that share physical pins with other signals.

Figure 1. Block diagram