POWER — Power control

The POWER module provides an interface to tasks, events, interrupt, and reset related configuration settings of the power management unit.

Note: Registers INTEN, INTENSET, and INTENCLR are the same registers (at the same address) as corresponding registers in CLOCK — Clock control.

Registers

Instances


Instance	Base address	TrustZone			Split access	Description
Instance	Base address	Map	Att	DMA	Split access	Description
POWER : S POWER : NS	0x50005000 0x40005000	US	NS	NA	No	Power control

Register overview


Register	Offset	Description
TASKS_CONSTLAT	0x78	Enable constant latency mode.
TASKS_LOWPWR	0x7C	Enable low power mode (variable latency)
SUBSCRIBE_CONSTLAT	0xF8	Subscribe configuration for task CONSTLAT
SUBSCRIBE_LOWPWR	0xFC	Subscribe configuration for task LOWPWR
EVENTS_POFWARN	0x108	Power failure warning
EVENTS_SLEEPENTER	0x114	CPU entered WFI/WFE sleep
EVENTS_SLEEPEXIT	0x118	CPU exited WFI/WFE sleep
PUBLISH_POFWARN	0x188	Publish configuration for event POFWARN
PUBLISH_SLEEPENTER	0x194	Publish configuration for event SLEEPENTER
PUBLISH_SLEEPEXIT	0x198	Publish configuration for event SLEEPEXIT
INTEN	0x300	Enable or disable interrupt
INTENSET	0x304	Enable interrupt
INTENCLR	0x308	Disable interrupt
RESETREAS	0x400	Reset reason
POWERSTATUS	0x440	Modem domain power status
GPREGRET[n]	0x51C	General purpose retention register
LTEMODEM.STARTN	0x610	Start LTE modem
LTEMODEM.FORCEOFF	0x614	Force off LTE modem

TASKS_CONSTLAT

Address offset: 0x78

Enable constant latency mode.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_CONSTLAT										Enable constant latency mode.
			Trigger	1								Trigger task

TASKS_LOWPWR

Address offset: 0x7C

Enable low power mode (variable latency)


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	W	TASKS_LOWPWR										Enable low power mode (variable latency)
			Trigger	1								Trigger task

SUBSCRIBE_CONSTLAT

Address offset: 0xF8

Subscribe configuration for task CONSTLAT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task CONSTLAT will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

SUBSCRIBE_LOWPWR

Address offset: 0xFC

Subscribe configuration for task LOWPWR


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that task LOWPWR will subscribe to
B	RW	EN
			Disabled	0								Disable subscription
			Enabled	1								Enable subscription

EVENTS_POFWARN

Address offset: 0x108

Power failure warning


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_POFWARN										Power failure warning
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_SLEEPENTER

Address offset: 0x114

CPU entered WFI/WFE sleep


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_SLEEPENTER										CPU entered WFI/WFE sleep
			NotGenerated	0								Event not generated
			Generated	1								Event generated

EVENTS_SLEEPEXIT

Address offset: 0x118

CPU exited WFI/WFE sleep


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	EVENTS_SLEEPEXIT										CPU exited WFI/WFE sleep
			NotGenerated	0								Event not generated
			Generated	1								Event generated

PUBLISH_POFWARN

Address offset: 0x188

Publish configuration for event POFWARN


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event POFWARN will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_SLEEPENTER

Address offset: 0x194

Publish configuration for event SLEEPENTER


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event SLEEPENTER will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

PUBLISH_SLEEPEXIT

Address offset: 0x198

Publish configuration for event SLEEPEXIT


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID				B																								A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	CHIDX		[0..255]								DPPI channel that event SLEEPEXIT will publish to
B	RW	EN
			Disabled	0								Disable publishing
			Enabled	1								Enable publishing

INTEN

Address offset: 0x300

Enable or disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													E	D			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	POFWARN										Enable or disable interrupt for event POFWARN
			Disabled	0								Disable
			Enabled	1								Enable
D	RW	SLEEPENTER										Enable or disable interrupt for event SLEEPENTER
			Disabled	0								Disable
			Enabled	1								Enable
E	RW	SLEEPEXIT										Enable or disable interrupt for event SLEEPEXIT
			Disabled	0								Disable
			Enabled	1								Enable

INTENSET

Address offset: 0x304

Enable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													E	D			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	POFWARN										Write '1' to enable interrupt for event POFWARN
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	SLEEPENTER										Write '1' to enable interrupt for event SLEEPENTER
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	SLEEPEXIT										Write '1' to enable interrupt for event SLEEPEXIT
			Set	1								Enable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

INTENCLR

Address offset: 0x308

Disable interrupt


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																													E	D			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	POFWARN										Write '1' to disable interrupt for event POFWARN
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
D	RW	SLEEPENTER										Write '1' to disable interrupt for event SLEEPENTER
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled
E	RW	SLEEPEXIT										Write '1' to disable interrupt for event SLEEPEXIT
			Clear	1								Disable
			Disabled	0								Read: Disabled
			Enabled	1								Read: Enabled

RESETREAS

Address offset: 0x400

Reset reason

Note: Unless cleared, the RESETREAS register will be cumulative. A field is cleared by writing '1' to it. If none of the reset sources are flagged, this indicates that the chip was reset from the on-chip reset generator, which will indicate a power-on reset or a brownout reset.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																	G	F	E												D		C	B	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	RESETPIN										Reset from pin reset detected
			NotDetected	0								Not detected
			Detected	1								Detected
B	RW	DOG										Reset from global watchdog detected
			NotDetected	0								Not detected
			Detected	1								Detected
C	RW	OFF										Reset due to wakeup from System OFF mode, when wakeup is triggered by DETECT signal from GPIO
			NotDetected	0								Not detected
			Detected	1								Detected
D	RW	DIF										Reset due to wakeup from System OFF mode, when wakeup is triggered by entering debug interface mode
			NotDetected	0								Not detected
			Detected	1								Detected
E	RW	SREQ										Reset from AIRCR.SYSRESETREQ detected
			NotDetected	0								Not detected
			Detected	1								Detected
F	RW	LOCKUP										Reset from CPU lock-up detected
			NotDetected	0								Not detected
			Detected	1								Detected
G	RW	CTRLAP										Reset triggered through CTRL-AP
			NotDetected	0								Not detected
			Detected	1								Detected

POWERSTATUS

Address offset: 0x440

Modem domain power status


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	R	LTEMODEM										LTE modem domain status
			OFF	0								LTE modem domain is powered off
			ON	1								LTE modem domain is powered on

GPREGRET[n] (n=0..1)

Address offset: 0x51C + (n × 0x4)

General purpose retention register


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																												A	A	A	A	A	A	A	A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	GPREGRET										General purpose retention register This register is a retained register

LTEMODEM

LTE Modem

LTEMODEM.STARTN

Address offset: 0x610

Start LTE modem

Note: Starting and stopping LTE modem must only be done through the LTE modem API to guarantee correct sequence in FW and HW and to avoid possible malfunctions.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000001				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
ID	R/W	Field	Value ID	Value								Description
A	RW	STARTN										Start LTE modem
			Start	0								Start LTE modem
			Hold	1								Hold LTE modem disabled

LTEMODEM.FORCEOFF

Address offset: 0x614

Force off LTE modem

Note: Starting and stopping LTE modem must only be done through the LTE modem API to guarantee correct sequence in FW and HW and to avoid possible malfunctions.


Bit number				31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ID																																			A
Reset 0x00000000				0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
ID	R/W	Field	Value ID	Value								Description
A	RW	FORCEOFF										Force off LTE modem
			Release	0								Release force off
			Hold	1								Hold force off active