Power management

The two internal modes are handled by the power management unit (PMU), whereas the external is handled by the user via the ENABLE pin.

The System Disabled mode provides a way to override the PMU by manipulating voltages presented to the ENABLE pin.

The PMU steers system-wide clock and power in order to provide the power modes - System ON and System OFF. Under the various modes, internal blocks are automatically powered by the PMU as required by the application.

The entire device can be powered down by presenting the appropriate voltage to the externally available ENABLE pin.

The nRF9161 provides a feature to be able disable power throughout the entire device externally. This can be useful when the device is operating as slave processor where it does not need to be powered on at all times, then it is possible to avoid unnecesary current leaking by driving the ENABLE pin to low. The nRF9161 will not start if is not enabled. Moreover, a change from disable to enable, will result in a power-on-reset behavior inside the device.

System OFF is the deepest internal power saving mode the system can enter.

In this mode, the core system functionality is powered down and ongoing tasks terminated, and only the reset and the wakeup functions are available and responsive.

The device is put into System OFF mode using the REGULATORS register interface. When in System OFF mode, one of the following signals/actions will wake up the device:

1. DETECT signal, generated by the GPIO peripheral
2. RESET
3. Debug session start

When the device wakes up from System OFF mode, a system reset is performed.

One or more RAM blocks can be retained in System OFF mode depending on the settings in the RAM[n].POWER registers in VMC. RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually overwritten by the startup code provided with the nRF application examples.

Before entering System OFF mode, the user must make sure that all on-going EasyDMA transactions have completed. This can be done by making sure that EasyDMA enabled peripherals have stopped and END events from them received. The LTE modem must also be stopped, by issuing a command through the modem API, before entering System OFF mode. Once the command is issued, wait for the modem to respond that it actually has stopped, as there may be a delay until the modem is disconnected from the network.

If the device is in debug interface mode, System OFF will be emulated to ensure that all resources required for debugging are available during System OFF.

See Debug and trace chapter for more information. Resources required for debugging include the following key components: Debug and trace, CLOCK — Clock control, POWER — Power control, NVMC — Non-volatile memory controller, CPU, flash, and RAM. To prevent the CPU from executing unwanted code, an infinite loop must be added directly after entering System OFF mode.

System ON is the power mode entered after a power-on reset.

The low power mode is default after power-on reset.

In low power mode, whenever no application or wireless activity takes place, function blocks like the application CPU, LTE modem and all peripherals are in IDLE state. That particular state is referred to as System ON IDLE. In this state, all function blocks retain their state and configuration, so they are ready to become active once configured by the CPU.

If any application or modem activity occurs, the system leaves the System ON IDLE state. Once a given activity in a function block is completed, the system automatically returns to IDLE, retaining its configuration.

As long as the system resides in low power mode, the PMU ensures that the appropriate regulators and clock sources are started or stopped based on the needs of the function blocks active at any given time.

This automatic power management can be overridden by switching to constant latency mode. In this mode, the CPU wakeup latency and the PPI task response are constant and kept at a minimum. This is secured by keeping a set of base resources that are always enabled. The advantage of having a constant and predictable latency will be at the cost of having significantly increased power consumption compared to the low power mode. The constant latency mode is enabled by triggering the CONSTLAT task (TASKS_CONSTLAT).

While the system is in constant latency mode, the low power mode can be enabled by triggering LOWPWR task (TASKS_LOWPWR).

To reduce power consumption while in System ON IDLE, RAM blocks can be turned off in System ON mode while enabling the retention of these RAM blocks in RAM[n].POWER registers in VMC. RAM[n].POWER are retained registers, see Reset behavior. Note that these registers are usually overwritten by the startup code provided with the nRF application examples.