Pin assignments

This section describes the pin assignment and the pin functions of the nRF9161.

The device provides flexibility when it comes to routing and configuration of the GPIO pins. However, for some pins there are recommendations on pin usage and configuration. See following table for more information about this.

LGA pin assignments

The pin assignment table and figure describe the assignments.

Figure 1. LGA pin assignments, top view

Table 1. LGA pin assignments
Pin no	Pin name	Function	Description
1	GND	Power	Ground
2	P0.05	Digital I/O (SoC)	General purpose I/O
3	P0.06	Digital I/O (SoC)	General purpose I/O
4	P0.07	Digital I/O (SoC)	General purpose I/O
5	GND	Power	Ground
6	GND	Power	Ground
7	GND	Power	Ground
8	GND	Power	Ground
9	GND	Power	Ground
10	RES		Do not connect/reserved for future use
11	GND	Power	Ground
12	VDD_GPIO	Power	GPIO power supply input and logic level
13	DEC0	Power	Power supply decoupling. Reserved for Nordic use.
14	GND	Power	Ground
15	P0.08	Digital I/O (SoC)	General purpose I/O
16	P0.09	Digital I/O (SoC)	General purpose I/O
17	GND	Power	Ground
18	P0.10	Digital I/O (SoC)	General purpose I/O
19	P0.11	Digital I/O (SoC)	General purpose I/O
20	P0.12	Digital I/O (SoC)	General purpose I/O
21	GND	Power	Ground
22	VDD2	Power	Supply voltage input
23	P0.13 AIN0	Digital I/O (SoC) Analog input	General purpose I/O Analog input
24	P0.14 AIN1	Digital I/O (SoC) Analog input	General purpose I/O Analog input
25	P0.15 AIN2	Digital I/O (SoC) Analog input	General purpose I/O Analog input
26	P0.16 AIN3	Digital I/O (SoC) Analog input	General purpose I/O Analog input
27	GND	Power	Ground
28	P0.17 AIN4	Digital I/O (SoC) Analog input	General purpose I/O Analog input
29	P0.18 AIN5	Digital I/O (SoC) Analog input	General purpose I/O Analog input
30	P0.19 AIN6	Digital I/O (SoC) Analog input	General purpose I/O Analog input
31	GND	Power	Ground
32	nRESET	Digital I/O (SoC)	SoC reset pin ¹^,²
33	SWDCLK	Digital input	Serial wire debug clock input for debug and programming
34	SWDIO	Digital I/O	Serial wire debug I/O for debug and programming
35	P0.20 AIN7	Digital I/O (SoC) Analog input	General purpose I/O Analog input
36	GND	Power	Ground
37	P0.21 TRACECLK	Digital I/O (SoC) Trace clock	General purpose I/O Trace buffer clock (optional)
38	P0.22 TRACEDATA[0]	Digital I/O (SoC) Trace data	General purpose I/O Trace buffer TRACEDATA[0] (optional)
39	P0.23 TRACEDATA[1]	Digital I/O (SoC) Trace data	General purpose I/O Trace buffer TRACEDATA[1] (optional)
40	P0.24 TRACEDATA[2]	Digital I/O (SoC) Trace data	General purpose I/O Trace buffer TRACEDATA[2] (optional)
41	GND	Power	Ground
42	P0.25 TRACEDATA[3]	Digital I/O (SoC) Trace data	General purpose I/O Trace buffer TRACEDATA[3] (optional)
43	SIM_RST	Digital I/O (SoC)	SIM reset
44	GND	Power	Ground
45	SIM_DET	Digital I/O (SoC)	SIM detect Not used. Must be left floating.
46	SIM_CLK	Digital I/O (SoC)	SIM clock
47	GND	Power	Ground
48	SIM_IO	Digital I/O (SoC)	SIM data
49	SIM_1V8	Power	SIM 1.8 V power supply output
50	GND	Power	Ground
51	RES		Do not connect/reserved for future use
52	GND	Power	Ground
53	MAGPIO2	Digital I/O (SoC)	1.8 V general purpose I/O
54	MAGPIO1	Digital I/O (SoC)	1.8 V general purpose I/O
55	MAGPIO0	Digital I/O (SoC)	1.8 V general purpose I/O
56	GND	Power	Ground
57	VIO	Power	MIPI RFFE control interface
58	SCLK	Digital I/O (SoC)	MIPI RFFE control interface
59	SDATA	Digital I/O (SoC)	MIPI RFFE control interface
60	GND	Power	Ground
61	ANT	RF	Single-ended 50 Ω LTE antenna pin
62	GND	Power	Ground
63	GND	Power	Ground
64	AUX	RF	Single-ended 50 Ω ANT loop-back pin
65	GND	Power	Ground
66	GND	Power	Ground
67	GPS	RF	Single-ended 50 Ω GPS input pin
68	GND	Power	Ground
69	GND	Power	Ground
70	RES		Do not connect/reserved for future use
71	RES		Do not connect/reserved for future use
72	GND	Power	Ground
73	RES		Do not connect/reserved for future use
74	GND	Power	Ground
75	GND	Power	Ground
76	GND	Power	Ground
77	GND	Power	Ground
78	GND	Power	Ground
79	GND	Power	Ground
80	GND	Power	Ground
81	GND	Power	Ground
82	GND	Power	Ground
83	P0.26	Digital I/O (SoC)	General purpose I/O
84	P0.27	Digital I/O (SoC)	General purpose I/O
85	GND	Power	Ground
86	P0.28	Digital I/O (SoC)	General purpose I/O
87	P0.29	Digital I/O (SoC)	General purpose I/O
88	P0.30	Digital I/O (SoC)	General purpose I/O
89	P0.31	Digital I/O (SoC)	General purpose I/O
90	GND	Power	Ground
91	COEX2	Digital I/O (SoC)	Coexistence interface
92	COEX1	Digital I/O (SoC)	Coexistence interface
93	COEX0	Digital I/O (SoC)	Coexistence interface
94	GND	Power	Ground
95	P0.00	Digital I/O (SoC)	General purpose I/O
96	P0.01	Digital I/O (SoC)	General purpose I/O
97	P0.02	Digital I/O (SoC)	General purpose I/O
98	GND	Power	Ground
99	P0.03	Digital I/O (SoC)	General purpose I/O
100	P0.04	Digital I/O (SoC)	General purpose I/O
101	ENABLE		Enable for the SiP internal regulator for the nRF91 SoC. Note: The nRF91 will not start until this pin is enabled.
102	VDD1	Power	Supply voltage
103	GND	Power	Ground
104-127	RES		Do not connect/reserved for future use

¹ External pull-up not allowed.

² For implementations that require the ERASEALL functionality, enable access to the nRESET pin. See Erase all for more information.