RP2040

A microcontroller
by Raspberry Pi

Colophon

© 2020-2025 Raspberry Pi Ltd (formerly Raspberry Pi (Trading) Ltd.)

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build-date: 2025-02-20

build-version: 3184e62-clean

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Table of contents

Colophon .....1
Legal disclaimer notice .....1
1. Introduction .....8
1.1. Why is the chip called RP2040? .....8
1.2. Summary .....9
1.3. The Chip .....9
1.4. Pinout Reference .....10
1.4.1. Pin Locations .....10
1.4.2. Pin Descriptions .....11
1.4.3. GPIO Functions .....12
2. System Description .....14
2.1. Bus Fabric .....14
2.1.1. AHB-Lite Crossbar .....15
2.1.2. Atomic Register Access .....17
2.1.3. APB Bridge .....17
2.1.4. Narrow IO Register Writes .....17
2.1.5. List of Registers .....18
2.2. Address Map .....24
2.2.1. Summary .....24
2.2.2. Detail .....24
2.3. Processor subsystem .....26
2.3.1. SIO .....27
2.3.2. Interrupts .....60
2.3.3. Event Signals .....61
2.3.4. Debug .....61
2.4. Cortex-M0+ .....62
2.4.1. Features .....62
2.4.2. Functional Description .....64
2.4.3. Programmer's model .....68
2.4.4. System control .....73
2.4.5. NVIC .....74
2.4.6. MPU .....76
2.4.7. Debug .....76
2.4.8. List of Registers .....77
2.5. DMA .....91
2.5.1. Configuring Channels .....91
2.5.2. Starting Channels .....93
2.5.3. Data Request (DREQ) .....95
2.5.4. Interrupts .....96
2.5.5. Additional Features .....96
2.5.6. Example Use Cases .....97
2.5.7. List of Registers .....101
2.6. Memory .....120
2.6.1. ROM .....120
2.6.2. SRAM .....121
2.6.3. Flash .....122
2.7. Boot Sequence .....128
2.8. Bootrom .....128
2.8.1. Processor Controlled Boot Sequence .....129
2.8.2. Launching Code On Processor Core 1 .....131
2.8.3. Bootrom Contents .....132
2.8.4. USB Mass Storage Interface .....143
2.8.5. USB PICOBOT Interface .....144
2.9. Power Supplies .....150
2.9.1. Digital IO Supply (IOVDD) .....151
2.9.2. Digital Core Supply (DVDD)151
2.9.3. On-Chip Voltage Regulator Input Supply (VREG_VIN)151
2.9.4. USB PHY Supply (USB_VDD)151
2.9.5. ADC Supply (ADC_AVDD)152
2.9.6. Power Supply Sequencing152
2.9.7. Power Supply Schemes152
2.10. Core Supply Regulator155
2.10.1. Application Circuit155
2.10.2. Operating Modes156
2.10.3. Output Voltage Select157
2.10.4. Status157
2.10.5. Current Limit157
2.10.6. List of Registers157
2.10.7. Detailed Specifications160
2.11. Power Control160
2.11.1. Top-level Clock Gates160
2.11.2. SLEEP State161
2.11.3. DORMANT State161
2.11.4. Memory Power Down161
2.11.5. Programmer's Model162
2.12. Chip-Level Reset163
2.12.1. Overview163
2.12.2. Power-on Reset164
2.12.3. Brown-out Detection165
2.12.4. Supply Monitor167
2.12.5. External Reset167
2.12.6. Rescue Debug Port Reset167
2.12.7. Source of Last Reset168
2.12.8. List of Registers168
2.13. Power-On State Machine168
2.13.1. Overview168
2.13.2. Power On Sequence168
2.13.3. Register Control169
2.13.4. Interaction with Watchdog169
2.13.5. List of Registers169
2.14. Subsystem Resets172
2.14.1. Overview172
2.14.2. Programmer's Model173
2.14.3. List of Registers175
2.15. Clocks178
2.15.1. Overview178
2.15.2. Clock sources179
2.15.3. Clock Generators183
2.15.4. Frequency Counter186
2.15.5. Resus187
2.15.6. Programmer's Model187
2.15.7. List of Registers194
2.16. Crystal Oscillator (XOSC)216
2.16.1. Overview216
2.16.2. Usage217
2.16.3. Startup Delay217
2.16.4. XOSC Counter217
2.16.5. DORMANT mode218
2.16.6. Programmer's Model218
2.16.7. List of Registers219
2.17. Ring Oscillator (ROSC)221
2.17.1. Overview221
2.17.2. ROSC/XOSC trade-offs222
2.17.3. Modifying the frequency222
2.17.4. ROSC divider223
2.17.5. Random Number Generator223
2.17.6. ROSC Counter223
2.17.7. DORMANT mode223
2.17.8. List of Registers224
2.18. PLL228
2.18.1. Overview228
2.18.2. Calculating PLL parameters228
2.18.3. Configuration232
2.18.4. List of Registers234
2.19. GPIO236
2.19.1. Overview236
2.19.2. Function Select237
2.19.3. Interrupts239
2.19.4. Pads240
2.19.5. Software Examples241
2.19.6. List of Registers244
2.20. Sysinfo305
2.20.1. Overview305
2.20.2. List of Registers305
2.21. Syscfg306
2.21.1. Overview306
2.21.2. List of Registers306
2.22. TBMAN309
2.22.1. List of Registers309
3. PIO311
3.1. Overview311
3.2. Programmer's Model312
3.2.1. PIO Programs312
3.2.2. Control Flow313
3.2.3. Registers314
3.2.4. Stalling317
3.2.5. Pin Mapping318
3.2.6. IRQ Flags318
3.2.7. Interactions Between State Machines318
3.3. PIO Assembler (pioasm)319
3.3.1. Directives319
3.3.2. Values320
3.3.3. Expressions320
3.3.4. Comments320
3.3.5. Labels320
3.3.6. Instructions321
3.3.7. Pseudoinstructions321
3.4. Instruction Set321
3.4.1. Summary321
3.4.2. JMP322
3.4.3. WAIT323
3.4.4. IN324
3.4.5. OUT325
3.4.6. PUSH326
3.4.7. PULL327
3.4.8. MOV328
3.4.9. IRQ329
3.4.10. SET330
3.5. Functional Details331
3.5.1. Side-set331
3.5.2. Program Wrapping332
3.5.3. FIFO Joining334
3.5.4. Autopush and Autopull335
3.5.5. Clock Dividers339
3.5.6. GPIO Mapping340
3.5.7. Forced and EXEC'd Instructions342
3.6. Examples344
3.6.1. Duplex SPI344
3.6.2. WS2812 LEDs348
3.6.3. UART TX350
3.6.4. UART RX352
3.6.5. Manchester Serial TX and RX355
3.6.6. Differential Manchester (BMC) TX and RX357
3.6.7. I2C361
3.6.8. PWM364
3.6.9. Addition366
3.6.10. Further Examples367
3.7. List of Registers368
4. Peripherals383
4.1. USB383
4.1.1. Overview383
4.1.2. Architecture384
4.1.3. Programmer's Model394
4.1.4. List of Registers398
References417
4.2. UART417
4.2.1. Overview417
4.2.2. Functional description418
4.2.3. Operation420
4.2.4. UART hardware flow control422
4.2.5. UART DMA Interface424
4.2.6. Interrupts425
4.2.7. Programmer's Model427
4.2.8. List of Registers429
4.3. I2C440
4.3.1. Features440
4.3.2. IP Configuration441
4.3.3. I2C Overview441
4.3.4. I2C Terminology443
4.3.5. I2C Behaviour444
4.3.6. I2C Protocols445
4.3.7. Tx FIFO Management and START, STOP and RESTART Generation448
4.3.8. Multiple Master Arbitration450
4.3.9. Clock Synchronization451
4.3.10. Operation Modes452
4.3.11. Spike Suppression457
4.3.12. Fast Mode Plus Operation458
4.3.13. Bus Clear Feature458
4.3.14. IC_CLK Frequency Configuration459
4.3.15. DMA Controller Interface463
4.3.16. Operation of Interrupt Registers464
4.3.17. List of Registers464
4.4. SPI501
4.4.1. Overview502
4.4.2. Functional Description502
4.4.3. Operation505
4.4.4. List of Registers515
4.5. PWM521
4.5.1. Overview521
4.5.2. Programmer's Model522
4.5.3. List of Registers529
4.6. Timer534
4.6.1. Overview534
4.6.2. Counter535
4.6.3. Alarms535
4.6.4. Programmer's Model536
4.6.5. List of Registers539
4.7. Watchdog544
4.7.1. Overview544
4.7.2. Tick generation544
4.7.3. Watchdog Counter545
4.7.4. Scratch Registers545
4.7.5. Programmer's Model545
4.7.6. List of Registers547
4.8. RTC548
4.8.1. Storage Format548
4.8.2. Leap year549
4.8.3. Interrupts549
4.8.4. Reference clock549
4.8.5. Programmer's Model550
4.8.6. List of Registers553
4.9. ADC and Temperature Sensor557
4.9.1. ADC controller558
4.9.2. SAR ADC559
4.9.3. ADC ENOB561
4.9.4. INL and DNL562
4.9.5. Temperature Sensor563
4.9.6. List of Registers564
4.10. SSI567
4.10.1. Overview568
4.10.2. Features568
4.10.3. IP Modifications569
4.10.4. Clock Ratios570
4.10.5. Transmit and Receive FIFO Buffers571
4.10.6. 32-Bit Frame Size Support572
4.10.7. SSI Interrupts572
4.10.8. Transfer Modes573
4.10.9. Operation Modes574
4.10.10. Partner Connection Interfaces579
4.10.11. DMA Controller Interface595
4.10.12. APB Interface597
4.10.13. List of Registers598
5. Electrical and Mechanical607
5.1. Package607
5.1.1. Thermal characteristics608
5.1.2. Recommended PCB Footprint608
5.1.3. Package markings608
5.2. Storage conditions609
5.3. Solder profile609
5.4. Compliance611
5.5. Pinout611
5.5.1. Pin Locations611
5.5.2. Pin Definitions612
5.5.3. Pin Specifications614
5.6. Power Supplies622
5.7. Power Consumption622
5.7.1. Peripheral power consumption622
5.7.2. Power consumption for typical user cases623
Appendix A: Register Field Types625
Standard types625
RW:625
RO:625
WO:625
Clear types625
SC625
WC .....625
FIFO types .....626
RWF .....626
RF .....626
WF .....626
Appendix B: Errata .....627
Bootrom .....627
RP2040-E9 .....627
RP2040-E14 .....627
Clocks .....628
RP2040-E7 .....628
RP2040-E10 .....628
DMA .....629
RP2040-E12 .....629
RP2040-E13 .....629
GPIO / ADC .....630
RP2040-E6 .....630
RP2040-E11 .....630
USB .....630
RP2040-E2 .....630
RP2040-E3 .....631
RP2040-E4 .....631
RP2040-E5 .....631
RP2040-E15 .....633
RP2040-E16 .....634
Watchdog .....634
RP2040-E1 .....634
XIP Flash .....635
RP2040-E8 .....635
Appendix C: Availability .....636
Support .....636
Ordering code .....636
Documentation Release History .....637
20 February 2025 .....637
15 October 2024 .....637
02 May 2024 .....637
02 February 2024 .....637
14 June 2023 .....637
03 March 2023 .....637
01 December 2022 .....637
30 June 2022 .....638
17 June 2022 .....638
04 November 2021 .....638
03 November 2021 .....638
30 September 2021 .....638
23 June 2021 .....638
07 June 2021 .....639
13 April 2021 .....639
07 April 2021 .....639
05 March 2021 .....639
23 February 2021 .....639
01 February 2021 .....639
26 January 2021 .....639
21 January 2021 .....640

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