1. Introduction

Microcontrollers connect the world of software to the world of hardware. They allow developers to write software which interacts with the physical world in the same deterministic, cycle-accurate manner as digital logic. They occupy the bottom left corner of the price/performance space, outselling their more powerful brethren by a factor of ten to one. They are the workhorses that power the digital transformation of our world.

RP2040 is the debut microcontroller from Raspberry Pi. It brings our signature values of high performance, low cost, and ease of use to the microcontroller space.

With a large on-chip memory, symmetric dual-core processor complex, deterministic bus fabric, and rich peripheral set augmented with our unique Programmable I/O (PIO) subsystem, it provides professional users with unrivalled power and flexibility. With detailed documentation, a polished MicroPython port, and a UF2 bootloader in ROM, it has the lowest possible barrier to entry for beginner and hobbyist users.

RP2040 is a stateless device, with support for cached execute-in-place from external QSPI memory. This design decision allows you to choose the appropriate density of non-volatile storage for your application, and to benefit from the low pricing of commodity Flash parts.

RP2040 is manufactured on a modern 40nm process node, delivering high performance, low dynamic power consumption, and low leakage, with a variety of low-power modes to support extended-duration operation on battery power.

Key features:

• • Dual ARM Cortex-M0+ @ 133MHz
• • 264kB on-chip SRAM in six independent banks
• • Support for up to 16MB of off-chip Flash memory via dedicated QSPI bus
• • DMA controller
• • Fully-connected AHB crossbar
• • Interpolator and integer divider peripherals
• • On-chip programmable LDO to generate core voltage
• • 2 on-chip PLLs to generate USB and core clocks
• • 30 GPIO pins, 4 of which can be used as analogue inputs
• • Peripherals
  • ◦ 2 UARTs
  • ◦ 2 SPI controllers
  • ◦ 2 I2C controllers
  • ◦ 16 PWM channels
  • ◦ USB 1.1 controller and PHY, with host and device support
  • ◦ 8 PIO state machines

Whatever your microcontroller application, from machine learning to motor control, from agriculture to audio, RP2040 has the performance, feature set, and support to make your product fly.

1.1. Why is the chip called RP2040?

The post-fix numeral on RP2040 comes from the following,

1. 1. Number of processor cores (2)
2. 2. Loosely which type of processor (M0+)
3. 3. \( \text{floor}(\log_2(\text{RAM} / 16\text{kB})) \)
4. 4. \( \text{floor}(\log_2(\text{nonvolatile} / 128\text{kB})) \) or 0 if no onboard nonvolatile storage

see Figure 1 .

Figure 1. An explanation for the name of the RP2040 chip.

1.2. Summary

RP2040 is a low-cost, high-performance microcontroller device with flexible digital interfaces. Key features:

• • Dual Cortex M0+ processor cores, up to 133MHz (or 200MHz at 1.15V, see Section 2.15.3 )
• • 264kB of embedded SRAM in 6 banks
• • 30 multifunction GPIO
• • 6 dedicated IO for SPI Flash (supporting XIP)
• • Dedicated hardware for commonly used peripherals
• • Programmable IO for extended peripheral support
• • 4 channel ADC with internal temperature sensor, 500ksps, 12-bit conversion
• • USB 1.1 Host/Device

1.3. The Chip

RP2040 has a dual M0+ processor cores, DMA, internal memory and peripheral blocks connected via AHB/APB bus fabric.

Figure 2. A system overview of the RP2040 chip

Code may be executed directly from external memory through a dedicated SPI, DSPI or QSPI interface. A small cache improves performance for typical applications.

Debug is available via the SWD interface.

Internal SRAM can contain code or data. It is addressed as a single 264 kB region, but physically partitioned into 6 banks to allow simultaneous parallel access from different masters.

DMA bus masters are available to offload repetitive data transfer tasks from the processors.

GPIO pins can be driven directly, or from a variety of dedicated logic functions.

Dedicated hardware for fixed functions such as SPI, I2C, UART.

Flexible configurable PIO controllers can be used to provide a wide variety of IO functions.

A USB controller with embedded PHY can be used to provide FS/LS Host or Device connectivity under software control.

Four ADC inputs which are shared with GPIO pins.

Two PLLs to provide a fixed 48MHz clock for USB or ADC, and a flexible system clock up to 133MHz.

An internal Voltage Regulator to supply the core voltage so the end product only needs supply the IO voltage.

1.4. Pinout Reference

This section provides a quick reference for pinout and pin functions. Full details, including electrical specifications and package drawings, can be found in Chapter 5 .

1.4.1. Pin Locations

10

Figure 3. RP2040
Pinout for QFN-56
7×7mm (reduced ePad
size)

1.4.2. Pin Descriptions

Table 1. The function of each pin is briefly described here. Full electrical specifications can be found in Chapter 5 .

1.4.3. GPIO Functions

Each individual GPIO pin can be connected to an internal peripheral via the GPIO functions defined below. Some internal peripheral connections appear in multiple places to allow some system level flexibility. SIO, PIO0 and PIO1 can connect to all GPIO pins and are controlled by software (or software controlled state machines) so can be used to implement many functions.

Table 2. General Purpose Input/Output (GPIO) Bank 0 Functions

Table 3. GPIO bank 0 function descriptions