5. Electrical and Mechanical

Physical and electrical details of the RP2040 chip.

5.1. Package

Figure 166. Top down view (left, top) and side view (right, top), along with bottom view (left, bottom) of the RP2040 QFN-56 package

NOTE

There is no standard size for the central GND pad (or ePad) with QFNs. However, the one on RP2040 is smaller than most. This means that standard 0.4mm QFN-56 footprints provided with CAD tools may need adjusting. This gives the opportunity to route between the central pad and the ones on the periphery, which can help with maintaining power and ground integrity on cheaper PCBs. See Minimal Design Example for an example.

NOTE

Leads have a matte Tin (Sn) finish. Annealing is done post-plating, baking at 150°C for 1 hour. Minimum thickness for lead plating is 8 micromns, and the intermediate layer material is CuFe2P (roughened Copper (Cu)).

5.1.1. Thermal characteristics

The thermal characteristics of the package are shown in Table 611.

Table 611. Thermal data for the RP2040 QFN 56 package.

5.1.2. Recommended PCB Footprint

Figure 167. Recommended PCB Footprint for the RP2040 QFN-56 package

Figure 168. Package marking format

Table 612. Marking requirements and dimensions

NOTE

At Line 3, Step 1, the "RP2-B2" marking denotes device name "RP2" and silicon revision "B2."

5.2. Storage conditions

In order to preserve the shelf and floor life of bare RP2040 devices, the recommended storage conditions in line with J-STD (020E & 033D) for RP2040 (classified MSL1) should be kept under 30°C and 85% relative humidity.

5.3. Solder profile

RP2040 is a Pb-free part, with a \( T_p \) value of 260°C.

All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (live-bug orientation). If parts are reflowed in other than the normal live-bug assembly reflow orientation (i.e., dead-bug), \( T_p \) shall be within \( \pm 2^\circ\text{C} \) of the live-bug \( T_p \) and still meet the \( T_c \) requirements; otherwise, the profile shall be adjusted to achieve the latter.

Figure 169.
Classification profile
(not to scale)

NOTE

Reflow profiles in this document are for classification/preconditioning, and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed based on specific process needs and board designs, and should not exceed the parameters in Table 613 .

Table 613. Solder
profile values

5.4. Compliance

RP2040 is compliant to Moisture Sensitivity Level 1.

RP2040 is compliant to the requirement of REACH Substances of Very High Concern (SVHC) that ECHA announced on 25 June 2020.

RP2040 is compliant to the requirement and standard of Controlled Environment-related Substance of RoHS directive (EU) 2011/65/EU and directive (EU) 2015/863.

Package Level reliability qualifications carried out on RP2040:

• • Temperature Cycling per JESD22-A104
• • HAST per JESD22-A110
• • HTSL per JESD22-A103

NOTE

A tin whiskers test is not performed as RP2040 is a bottom only termination device (QFN package) which not applicable to JEDEC standard (JESD201A).

5.5. Pinout

5.5.1. Pin Locations

Figure 170. RP2040
QFN-56 package
pinout

5.5.2. Pin Definitions

5.5.2.1. Pin Types

In the following GPIO Pin table (Table 615), the pin types are defined as shown below.

Table 614. Pin Types

5.5.2.2. Pin List

Table 615. GPIO pins

Table 616. QSPI pins

Table 617. Crystal oscillator pins

Table 618. Serial wire debug pins

Table 619. Miscellaneous pins

Table 620. USB pins

Table 621. Power supply pins

5.5.3. Pin Specifications

The following electrical specifications are obtained from characterisation over the specified temperature and voltage ranges, as well as process variation, unless the specification is marked as 'Simulated'. In this case, the data is for information purposes only, and is not guaranteed.

5.5.3.1. Absolute Maximum Ratings

Table 622. Absolute maximum ratings for digital IO (Standard and Fault Tolerant)

5.5.3.2. ESD Performance

Table 623. ESD performance for all pins, unless otherwise stated

5.5.3.3. Thermal Performance

Table 624. Thermal Performance

5.5.3.4. IO Electrical Characteristics

Table 625. Digital IO characteristics - Standard and FT unless otherwise stated

Table 626. USB IO characteristics

Table 627. ADC characteristics

Table 628. Oscillator pin characteristics when using a Square Wave input

See Section 2.16 for more details on the Oscillator, and Minimal Design Example for information on crystal usage.

5.5.3.5. Interpreting GPIO output voltage specifications

The GPIOs on RP2040 have four different output drive strengths, which are nominally called 2, 4, 8 and 12mA modes. These are not hard limits, nor do they mean that they will always be sourcing (or sinking) the selected amount of milliamps. The amount of current a GPIO sources or sinks is dependent on the load attached to it. It will attempt to drive the output to the IOVDD level (or 0V in the case of a logic 0), but the amount of current it is able to source is limited, which will be dependent on the selected drive strength. Therefore the higher the current load is, the lower the voltage will be at the pin. At some point, the GPIO will be sourcing so much current, that the voltage is so low, it won't be recognised as a logic 1 by the input of a connected device. The purpose of the output specifications in Table 625 are to try and quantify how much lower the voltage can be expected to be, when drawing specified amounts of current from the pin.

The Output High Voltage (V _OH ) is defined as the lowest voltage the output pin can be when driven to a logic 1 with a particular selected drive strength; e.g., 4mA being sourced by the pin whilst in 4mA drive strength mode. The Output Low Voltage is similar, but with a logic 0 being driven.

In addition to this, the sum of all the IO currents being sourced (i.e. when outputs are being driven high) from the IOVDD bank (essentially the GPIO and QSPI pins), must not exceed I _{IOVDD_MAX} . Similarly, the sum of all the IO currents being sunk (i.e. when the outputs are being driven low) must not exceed I _{IOVSS_MAX} .

Figure 171. Typical Current vs Voltage curves of a GPIO output.

Figure 171 shows the effect on the output voltage as the current load on the pin increases. You can clearly see the effect of the different drive strengths; the higher the drive strength, the closer the output voltage is to IOVDD (or 0V) for a given current. The minimum \( V_{OH} \) and maximum \( V_{OL} \) limits are shown in red. You can see that at the specified current for each drive strength, the voltage is well within the allowed limits, meaning that this particular device could drive a lot more current and still be within \( V_{OH}/V_{OL} \) specification. This is a typical part at room temperature, there will be a spread of other devices which will have voltages much closer to this limit. Of course, if your application doesn't need such tightly controlled voltages, then you can source or sink more current from the GPIO than the selected drive strength setting, but experimentation will be required to determine if it indeed safe to do so in your application, as it will be outside the scope of this specification.

5.5.3.6. Pin IO Delays

These delays include PIO's input/output mapping logic, IO muxing, and the actual pad delays into a nominal load of 5 pF. Min/max is over the extremes of process variation, voltage (1.1 V +/- 10%) and temperature (-40 C to 125 C).

These delays assume an IOVDD of 1.8 V, with PADS_VSEL set. At IOVDD = 3.3 V, the delay is significantly lower, and the range is smaller.

The flops themselves have a typical setup time of 10.6 ps and hold time of 2.2 ps. The IO delays between flops and pads must be taken into account.

For minimum and maximum output delays, from CLK_SYS arriving at any flop in PIO to the data being valid at a particular GPIO pad see Table 629.

Table 629. Pin minimum and maximum delays from flop to pad, in nanoseconds.

For minimum and maximum input delays, from pad input to the input synchroniser, see Table 630 .

Table 630. Pin minimum and maximum delays from pad input to input synchroniser, in nanoseconds.

For minimum and maximum input delays over all corners, from pad input to state machine IN data flops (synchronisers bypassed) see Table 631 .

Table 631. Pin minimum and maximum delays from pad input to state machine IN data flops (synchronisers bypassed), in nanoseconds.

5.5.3.6.1. Effects of IOVDD

All of the IO delays given above assume IOVDD = 1.8V. Increasing IOVDD to 3.3V reduces the pad delays quite significantly, and the pad delay is a large fraction of the delays reported above. See Table 632 for a summary of best and worst pad delays at 1.8V and 3.3V.

Table 632. Best and worst pad delays at 1.8V and 3.3V.

Changing IOVDD does not affect any logic in the core domain, so these differences can be added to the IO delay tables above to estimate the IO delay ranges at IOVDD = 3.3V (see Table 633 ).

Table 633. IO delay ranges at IOVDD = 3.3V.

5.6. Power Supplies

Table 634. Power Supply Specifications

^a If IOVDD <2.5V, GPIO VOLTAGE_SELECT registers should be adjusted accordingly. See Section 2.9 for details.

^b Short term transients should be within +/-100mV. If using 200MHz for clk_sys as described in Section 2.15.3 , set DVDD to 1.15V.

^c ADC performance will be compromised at voltages below 2.97V

5.7. Power Consumption

5.7.1. Peripheral power consumption

Baseline readings are taken with only clock sources and essential peripherals ( BUSCTRL , BUSFAB , VREG , Resets, ROM, SRAMs) active in the WAKE_EN0 / WAKE_EN1 registers. Clocks are set to default clock settings. Each peripheral is activated in turn by enabling all clock sources for the peripheral in the WAKE_EN0 / WAKE_EN1 registers. Current consumption is the increase in current when the peripheral clocks are enabled.

Table 635. Baseline power consumption

Because of fixed external reference clocks of 48 MHz, as well as the variable system clock input, ADC and USBCTRL power consumption does not vary linearly with system clock (as it does for other peripherals which only have system and/or peripheral clock inputs). Absolute DVDD current consumption of the ADC and USBCTRL blocks at standard clocks (system clock of 125 MHz) is given below:

Table 636. Baseline power consumption for ADC and USBCTRL

5.7.2. Power consumption for typical user cases

The following data shows the current consumption of various power supplies on 3 each of typical (tt), fast (ff) and slow (ss) corner RP2040 devices, with four different software use-cases.

Image: Note icon

For power consumption of the Raspberry Pi Pico, please see the Raspberry Pi Pico Datasheet .

Firstly, 'Popcorn' (Media player demo) using the VGA, SD Card, and Audio board. This demo uses VGA video, I2S audio and 4-bit SD Card access, with a system clock frequency of 48MHz.

Image: Note icon

For more details of the VGA board see the Hardware design with RP2040 book.

Secondly, the BOOTSEL mode of RP2040. These measurements are made both with and without USB activity on the bus, using a Raspberry Pi 4 as a host.

The third use-case uses the hello_dormant binary which puts RP2040 into a low power state, DORMANT mode.

The final use-case uses the hello_sleep binary code which puts RP2040 into a low power state, SLEEP mode.

Table 637 has two columns per power supply, 'Typical Average Current' and 'Maximum Average Current'. The former is the current averaged over several seconds that you might expect a typical RP2040 to consume at room temperature and nominal voltage (e.g., DVDD=1.1V, IOVDD=3.3V, etc). The 'Maximum Average Current' is the maximum current consumption (again averaged over several seconds) you might expect to see on a worst-case RP2040 device, across the temperature extremes, and maximum voltage (e.g., DVDD=1.21V, etc).

Image: Note icon

The 'Popcorn' consumption measurements depend on the video being displayed at the time. The 'Typical' values are obtained over several seconds of video, with varied colour and intensity. The 'Maximum' values are measured during periods of white video, when the required current is at its highest.

Table 637. Power Consumption

5.7.2.1. Power Consumption versus frequency

To give an indication of the relationship between the core frequency that RP2040 is operating at, and the current consumed by the DVDD supply, Figure 172 shows the measured results of a typical RP2040 device, continuously running FFT calculations on both cores, at various core clock frequencies. Figure 172 also shows the effects of case temperature, and DVDD voltage upon the current consumption.

Figure 172. DVDD Current vs Core Frequency of a typical RP2040 device, whilst running FFT calculations

Appendix A: Register Field Types

Standard types

RW:

• • Read/Write
• • Read operation returns the register value
• • Write operation updates the register value

RO:

• • Read-only
• • Read operation returns the register value
• • Write operations are ignored

WO:

• • Write-only
• • Read operation returns 0
• • Write operation updates the register value

Clear types

SC

• • Self-Clearing
• • Writing a 1 to a bit in an SC field will trigger an event, once the event is triggered the bit clears automatically
• • Writing a 0 to a bit in an SC field does nothing

WC

• • Write-Clear
• • Writing a 1 to a bit in a WC field will write that bit to 0
• • Writing a 0 to a bit in a WC field does nothing
• • Read operation returns the register value

FIFO types

These fields are used for reading and writing data to and from FIFOs. Accompanying registers provide FIFO control and status. There is no fixed format for the control and status registers, as they are specific to each FIFO interface.

RWF

• • Read/Write FIFO
• • Reading this field returns data from a FIFO
  • ◦ When the read is complete, the data value is removed from the FIFO
  • ◦ If the FIFO is empty, a default value will be returned; the default value is specific to each FIFO interface
• • Data written to this field is pushed to a FIFO, Behaviour when the FIFO is full is specific to each FIFO interface
• • Read and write operations may access different FIFOs

RF

• • Read FIFO
• • Functions the same as RWF, but read-only

WF

• • Write FIFO
• • Functions the same as RWF, but write-only

Appendix B: Errata

Hardware blocks are listed alphabetically. Errata are listed numerically under the relevant block.

Bootrom

RP2040-E9

RP2040-E14

Clocks

RP2040-E7

RP2040-E10

DMA

RP2040-E12

RP2040-E13

GPIO / ADC

RP2040-E6

RP2040-E11

USB

RP2040-E2

RP2040-E3

RP2040-E4

RP2040-E5

RP2040-E15

RP2040-E16

Watchdog

RP2040-E1

XIP Flash

RP2040-E8

Appendix C: Availability

Raspberry Pi understands the value to customers of long term availability of product and therefore aims to continue supply for as long as practically possible. We expect RP2040 to remain in production until at least January 2041.

Support

For support see the Pico section of the Raspberry Pi website , and post questions on the Raspberry Pi forum .

Ordering code

RP2040 can be ordered in bulk from Raspberry Pi Direct .

Table 638. Part Number

NOTE

RRP was correct at time of publication and excludes taxes.

Documentation Release History

20 February 2025

• • Updated register field types descriptions to use the improved RP2350 wording.
• • Add information about running Dual Cortex M0+ processor cores at 200MHz.

15 October 2024

• • Corrected minor typos and formatting issues.
• • Switched back to separate release histories per PDF.

02 May 2024

• • Corrected minor typos and formatting issues.

02 February 2024

• • Corrected minor typos and formatting issues.
• • Updated ROSC register information.
• • Updated to include the new recommended part number for crystals used with RP2040.

14 June 2023

• • Corrected minor typos and formatting issues.

03 March 2023

• • Corrected minor typos and formatting issues.
• • Added errata E15 .
• • Added package marking specifications.
• • Added RP2040 baseline power consumption figures.

01 December 2022

• • Corrected minor typos and formatting issues.
• • Added RP2040 availability information.
• • Added RP2040 storage conditions and thermal characteristics.

• • Replaced SDK library documentation with links to the online version.

30 June 2022

• • Corrected minor typos and formatting issues.

17 June 2022

• • Corrected minor typos and formatting issues.
• • RP2040 now qualified to -40°C, minimum operating temperature changed from -20°C to -40°C.
• • Increased PLL min VCO from 400MHz to 750MHz for improved stability across operating conditions.
• • Added errata E12 , E13 and E14 .

04 November 2021

• • Corrected minor typos and formatting issues.
• • Improved documentation on USB double buffering.
• • Updated links to documentation.

03 November 2021

• • Corrected minor typos and formatting issues.
• • Fixed some register access types and descriptions.
• • Added core 1 launch sequence info.
• • Described SDK "panic" handling.
• • Updated picotool documentation.

30 September 2021

• • Corrected minor typos and formatting issues.
• • Added information about B2 release.
• • Updated errata for B2 release.

23 June 2021

• • Corrected minor typos and formatting issues.
• • Updated information on ADC.
• • Added errata E11 .

07 June 2021

• • Corrected minor typos and formatting issues.
• • Added SDK release history.

13 April 2021

• • Corrected minor typos and formatting issues.
• • Clarified that all source code in the documentation is under the 3-Clause BSD license.

07 April 2021

• • Corrected minor typos and formatting issues.
• • Added errata E10 .

05 March 2021

• • Corrected minor typos and formatting issues.
• • Improved pinout diagram.

23 February 2021

• • Corrected minor typos and formatting issues.
• • Changed font.
• • Added additional documentation on sink/source limits for RP2040.
• • Made major improvements to SWD documentation.
• • Added errata E7 , E8 and E9 .

01 February 2021

• • Corrected minor typos and formatting issues.
• • Made small improvements to PIO documentation.
• • Added missing TIMER2 and TIMER3 registers to DMA.

26 January 2021

• • Corrected minor typos and formatting issues.
• • Added extra information about using DMA with ADC.
• • Clarified M0+ and SIO CPUID registers.
• • Added more discussion of Timers.

• • Renamed books and optimised size of output PDFs.

21 January 2021

• • Initial release.

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