1. Introduction

RP2350 is a new family of microcontrollers from Raspberry Pi that offers major enhancements over RP2040. Key features include:

• • Dual Cortex-M33 or Hazard3 processors at 150 MHz
• • 520 kB on-chip SRAM, in 10 independent banks
• • 8 kB of one-time-programmable storage (OTP)
• • Up to 16 MB of external QSPI flash or PSRAM through dedicated QSPI bus
• • Additional 16 MB flash or PSRAM through optional second chip-select
• • On-chip switched-mode power supply to generate core voltage
• • Optional low-quiescent-current LDO mode for sleep states
• • 2 × on-chip PLLs for internal or external clock generation
• • GPIOs are 5 V-tolerant (powered) and 3.3 V-failsafe (unpowered)
• • Security features:
  • ◦ Optional boot signing, enforced by on-chip mask ROM, with key fingerprint in OTP
  • ◦ Protected OTP storage for optional boot decryption key
  • ◦ Global bus filtering based on Arm or RISC-V security/privilege levels
  • ◦ Peripherals, GPIOs, and DMA channels individually assignable to security domains
  • ◦ Hardware mitigations for fault injection attacks
  • ◦ Hardware SHA-256 accelerator
• • Peripherals:
  • ◦ 2 × UARTs
  • ◦ 2 × SPI controllers
  • ◦ 2 × I2C controllers
  • ◦ 24 × PWM channels
  • ◦ USB 1.1 controller and PHY, with host and device support
  • ◦ 12 × PIO state machines
  • ◦ 1 × HSTX peripheral

Table 1 shows the RP2350 family of devices, including options for QFN-80 (10 × 10 mm) and QFN-60 (7 × 7 mm) packages, with and without flash-in-package.

Table 1. RP2350 device family

1.1. The chip

Dual Cortex-M33 or Hazard3 processors access RP2350's memory and peripherals via AHB and APB bus fabric.

Figure 1. A system overview of the RP2350 chip

Code may execute directly from external memory through a dedicated QSPI memory interface in the execute-in-place subsystem (XIP). The cache improves XIP performance significantly. Both flash and RAM can attach via this interface.

Debug is available via the SWD interface. This allows an external host to load, run, halt and inspect software running on the system, or configure the execution trace output.

Internal SRAM can contain code or data. It is addressed as a single 520 kB region, but physically partitioned into 10 banks to allow simultaneous parallel access from different managers. All SRAM supports single-cycle access.

A high-bandwidth system DMA offloads repetitive data transfer tasks from the processors.

GPIO pins can be driven directly via single-cycle IO (SIO), or from a variety of dedicated logic functions such as the hardware SPI, I2C, UART and PWM. Programmable IO controllers (PIO) can provide a wider variety of IO functions, or supplement the number of fixed-function peripherals.

A USB controller with embedded PHY provides FS/LS Host or Device connectivity under software control.

Four or eight ADC inputs (depending on package size) are shared with GPIO pins.

Two PLLs provide a fixed 48 MHz clock for USB or ADC, and a flexible system clock up to 150 MHz. A crystal oscillator provides a precise reference for the PLLs.

An internal voltage regulator supplies the core voltage, so you need generally only supply the IO voltage. It operates as a

switched mode buck converter when the system is awake, providing up to 200 mA at a variable output voltage, and can switch to a low-quiescent-current LDO mode when the system is asleep, providing up to 1 mA for state retention.

The system features low-power states where unused logic is powered off, supporting wakeup from timer or IO events. The amount of SRAM retained during power-down is configurable.

The internal 8 kB one-time-programmable storage (OTP) contains chip information such as unique identifiers, can be used to configure hardware and bootrom security features, and can be programmed with user-supplied code and data.

The built-in bootrom implements direct boot from flash or OTP, and serial boot from USB or UART. Code signature enforcement is supported for all boot media, using a key fingerprint registered in internal OTP storage. OTP can also store decryption keys for encrypted boot, preventing flash contents from being read externally.

RISC-V architecture support is implemented by dynamically swapping the Cortex-M33 (Armv8-M) processors with Hazard3 (RV32IMAC+) processors. Both architectures are available on all RP2350-family devices. The RISC-V cores support debug over SWD, and can be programmed with the same SDK as the Arm cores.

1.2. Pinout reference

This section provides a quick reference for pinout and pin functions. Full details, including electrical specifications and package drawings, can be found in Chapter 14 .

1.2.1. Pin locations

1.2.1.1. QFN-60 (RP2350A)

Figure 2. RP2350
Pinout for QFN-60
7×7mm (reduced ePad
size)

1.2.1.2. QFN-80 (RP2350B)

Figure 3. RP2350
Pinout for QFN-80
10×10mm (reduced
ePad size)

1.2.2. Pin descriptions

Table 2. The function
of each pin is briefly
described here. Full
electrical
specifications can be
found in Chapter 14 .

1.2.3. GPIO functions (Bank 0)

Each individual GPIO pin can be connected to an internal peripheral via the GPIO functions defined below. Some internal peripheral connections appear in multiple places to allow some system level flexibility. SIO, PIO0, PIO1 and PIO2 can connect to all GPIO pins and are controlled by software (or software controlled state machines) so can be used to implement many functions.

Table 3. General Purpose Input/Output (GPIO) Bank 0 Functions

Table 4. GPIO bank 0 function descriptions

NOTE

GPIOs 0 through 29 are available in all package variants. GPIOs 30 through 47 are available only in QFN-80 (RP2350B) package.

NOTE

Analogue input is available on GPIOs 26 through 29 in the QFN-60 package (RP2350A), for a total of four inputs, and on GPIOs 40 through 47 in the QFN-80 package (RP2350B), for a total of eight inputs.

1.2.4. GPIO functions (Bank 1)

GPIO functions are also available on the six dedicated QSPI pins, which are usually used for flash execute-in-place, and on the USB DP/DM pins. These may become available for general-purpose use depending on the use case, for example, QSPI pins may not be needed for code execution if RP2350 is booting from internal OTP storage, or being controlled externally via SWD.

Table 5. GPIO Bank 1 Functions

Table 6. GPIO bank 1 function descriptions

1.3. Why is the chip called RP2350?

Figure 4. An explanation for the name of the RP2350 chip.

The post-fix numeral on RP2350 comes from the following,

1. 1. Number of processor cores
   • ◦ 2 indicates a dual-core system
2. 2. Loosely which type of processor
   • ◦ 3 indicates Cortex-M33 or Hazard3
3. 3. Internal memory capacity: \( \log_2 \lfloor \frac{\text{RAM}}{16 \text{ kB}} \rfloor \)
   • ◦ 5 indicates at least \( 2^5 \times 16 \text{ kB} = 512 \text{ kB} \)
   • ◦ RP2350 has 520 kB of main system SRAM
4. 4. Internal storage capacity: \( \log_2 \lfloor \frac{\text{nonvolatile}}{128 \text{ kB}} \rfloor \) (or 0 if no onboard nonvolatile storage)

• ◦ RP2350 uses external flash
• ◦ RP2354 has \( 2^4 \times 128 \text{ kB} = 2 \text{ MB} \) of internal flash

1.4. Version History

Table 7 lists versions of RP2350. Later versions fix bugs in earlier versions. For more information about the changes made between versions, see Appendix C . Also refer to Product Change Notification (PCN) 28.

Table 7. RP2350
version history