12. Peripherals

12.1. UART

Arm documentation

Excerpted from the PrimeCell UART (PL011) Technical Reference Manual . Used with permission.

RP2350 has 2 identical instances of a UART peripheral, based on the Arm Primecell UART (PL011) (Revision r1p5).

Each instance supports the following features:

• • Separate 32×8 TX and 32×12 RX FIFOs
• • Programmable baud rate generator, clocked by clk_peri (see Figure 33 )
• • Standard asynchronous communication bits (start, stop, parity) added on transmit and removed on receive
• • Line break detection
• • Programmable serial interface (5, 6, 7, or 8 bits)
• • 1 or 2 stop bits
• • Programmable hardware flow control

Each UART can be connected to a number of GPIO pins as defined in the GPIO muxing table in Section 9.4 . Connections to the GPIO muxing use a prefix including the UART instance name uart0_ or uart1_ , and include the following:

• • Transmit data tx (referred to as UARTTXD in the following sections)
• • Received data rx (referred to as UARTRXD in the following sections)
• • Output flow control rts (referred to as nUARTRTS in the following sections)
• • Input flow control cts (referred to as nUARTCTS in the following sections)

The modem mode and IrDA mode of the PL011 are not supported.

The UARTCLK is driven from clk_peri , and PCLK is driven from the system clock clk_sys (see Figure 33 ).

12.1.1. Overview

The UART performs:

• • Serial-to-parallel conversion on data received from a peripheral device
• • Parallel-to-serial conversion on data transmitted to the peripheral device

The CPU reads and writes data and control/status information through the AMBA APB interface. The transmit and receive paths are buffered with internal FIFO memories that store up to 32 bytes independently in both transmit and receive modes.

The UART:

• • Includes a programmable baud rate generator that generates a common transmit and receive internal clock from the UART internal reference clock input, UARTCLK
• • Offers similar functionality to the industry-standard 16C650 UART device
• • Supports a maximum baud rate of UARTCLK / 16 in UART mode (7.8 Mbaud at 125MHz)

The UART operation and baud rate values are controlled by the Line Control Register ( UARTLCR_H ) and the baud rate divisor registers: Integer Baud Rate Register ( UARTIBRD ), and Fractional Baud Rate Register ( UARTFBRD ).

The UART can generate:

• • Individually maskable interrupts from the receive (including timeout), transmit, modem status and error conditions
• • A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked
• • DMA request signals for interfacing with a Direct Memory Access (DMA) controller

If a framing, parity, or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten.

You can program the FIFOs to be 1-byte deep providing a conventional double-buffered UART interface.

There is a programmable hardware flow control feature that uses the nUARTCTS input and the nUARTRTS output to automatically control the serial data flow.

12.1.2. Functional description

Figure 63. UART block diagram. Test logic is not shown for clarity.

12.1.2.3. Baud rate generator

The baud rate generator contains free-running counters that generate the internal clocks: Baud16 and IrLPBaud16 signals. Baud16 provides timing information for UART transmit and receive control. Baud16 is a stream of pulses with a width of one UARTCLK clock period and a frequency of 16 times the baud rate.

12.1.2.4. Transmit FIFO

The transmit FIFO is an 8-bit wide, 32 location deep, FIFO memory buffer. CPU data written across the APB interface is stored in the FIFO until read out by the transmit logic. When disabled, the transmit FIFO acts like a one byte holding register.

12.1.2.5. Receive FIFO

The receive FIFO is a 12-bit wide, 32 location deep, FIFO memory buffer. Received data and corresponding error bits are stored in the receive FIFO by the receive logic until read out by the CPU across the APB interface. When disabled, the receive FIFO acts like a one byte holding register.

12.1.2.6. Transmit logic

The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs the serial bit stream in the following order:

1. 1. Start bit
2. 2. Data bits (Least Significant Bit (LSB) first)
3. 3. Parity bit
4. 4. Stop bits according to the programmed configuration in control registers

12.1.2.7. Receive logic

The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Receive logic includes overrun, parity, frame error checking, and line break detection; you can find the output of these checks in the status that accompanies the data written to the receive FIFO.

12.1.2.8. Interrupt generation logic

The UART generates individual maskable active HIGH interrupts to the processor interrupt controllers. To generate combined interrupts, the UART outputs an OR function of the individual interrupt requests.

For more information, see Section 12.1.6 .

12.1.2.9. DMA interface

The UART provides an interface to connect to the DMA controller as a UART DMA; for more information, see Section 12.1.5 .

12.1.2.10. Synchronizing registers and logic

The UART supports both asynchronous and synchronous operation of the clocks, PCLK and UARTCLK . The UART implements always-on synchronisation registers and handshaking logic. This has a minimal impact on performance and area. The UART performs control signal synchronisation on both directions of data flow (from the PCLK to the UARTCLK domain, and from the UARTCLK to the PCLK domain).

12.1.3. Operation

12.1.3.1. Clock signals

The frequency selected for UARTCLK must accommodate the required range of baud rates:

• • \( \text{FUARTCLK (min)} \geq 16 \times \text{baud\_rate (max)} \)
• • \( \text{FUARTCLK (max)} \leq 16 \times 65535 \times \text{baud\_rate (min)} \)

For example, for a range of baud rates from 110 baud to 460800 baud the UARTCLK frequency must be between 7.3728MHz to 115.34MHz.

To use all baud rates, the UARTCLK frequency must fall within the required error limits.

There is also a constraint on the ratio of clock frequencies for PCLK to UARTCLK . The frequency of UARTCLK must be no more than 5/3 times faster than the frequency of PCLK :

• • \( \text{FUARTCLK} \leq 5/3 \times \text{FPCLK} \)

For example, in UART mode, to generate 921600 baud when UARTCLK is 14.7456MHz, PCLK must be greater than or equal to 8.85276MHz. This ensures that the UART has sufficient time to write the received data to the receive FIFO.

12.1.3.2. UART operation

Control data is written to the UART Line Control Register, UARTLCR . This register is 30 bits wide internally, but provides external access through the APB interface by writes to the following registers:

• • UARTLCR_H , which defines the following:
  • ◦ transmission parameters
  • ◦ word length
  • ◦ buffer mode
  • ◦ number of transmitted stop bits
  • ◦ parity mode
  • ◦ break generation
• • UARTIBRD , which defines the integer baud rate divider
• • UARTFBRD , which defines the fractional baud rate divider

12.1.3.2.1. Fractional baud rate divider

The baud rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The baud rate generator uses the baud rate divisor to determine the bit period. The fractional baud rate divider enables the use of any clock with a frequency greater than 3.6864MHz to act as UARTCLK , while it is still possible to generate all the standard baud rates.

The 16-bit integer is written to the Integer Baud Rate Register, UARTIBRD . The 6-bit fractional part is written to the Fractional Baud Rate Register, UARTFBRD . The Baud Rate Divisor has the following relationship to UARTCLK :

Baud Rate Divisor = \( \text{UARTCLK}/(16 \times \text{Baud Rate}) = BRD_I + BRD_F \) where \( BRD_I \) is the integer part and \( BRD_F \) is the fractional part separated by a decimal point as shown in Figure 64.

Figure 64. Baud rate divisor.

To calculate the 6-bit number ( \( m \) ), multiply the fractional part of the required baud rate divisor by 64 ( \( 2^n \) , where \( n \) is the width of the UARTFBRD register) and add 0.5 to account for rounding errors:

The UART generates an internal clock enable signal, Baud16. This is a stream of UARTCLK -wide pulses with an average frequency of 16 times the required baud rate. Divide this signal by 16 to give the transmit clock. A low number in the baud rate divisor produces a short bit period, and a high number in the baud rate divisor produces a long bit period.

12.1.3.2.2. Data transmission or reception

The UART uses two 32-byte FIFOs to store data received and transmitted. The receive FIFO has an extra four bits per character for status information. For transmission, data is written into the transmit FIFO. If the UART is enabled, it causes a data frame to start transmitting with the parameters indicated in the Line Control Register, UARTLCR_H . Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH immediately after data writes to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data transmits. BUSY is negated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though the UART might no longer be enabled.

For each sample of data, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined, and one sample is taken either side of it.

When the receiver is idle ( UARTRXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter in UART mode, or the fourth cycle of the counter in SIR mode to allow for the shorter logic 0 pulses (half way through a bit period).

The start bit is valid if UARTRXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is detected and it is ignored.

If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.

Lastly, a valid stop bit is confirmed if UARTRXD is HIGH, otherwise a framing error has occurred. When a full word is received, the data is stored in the receive FIFO, with any error bits associated with that word

12.1.3.2.3. Error bits

The receive FIFO stores three error bits in bits 8 (framing), 9 (parity), and 10 (break), each associated with a particular character. An additional error bit, stored in bit 11 of the receive FIFO, indicates an overrun error.

12.1.3.2.4. Overrun bit

The overrun bit is not associated with the character in the receive FIFO. The overrun error is set when the FIFO is full and the next character is completely received in the shift register. The data in the shift register is overwritten, but it is not written into the FIFO. When an empty location becomes available in the FIFO, another character is received and the state of the overrun bit is copied into the receive FIFO along with the received character. The overrun state is then cleared. Table 1025 lists the bit functions of the receive FIFO.

Table 1025. Receive
FIFO bit functions

12.1.3.2.5. Disabling the FIFOs

The bottom entry of the transmit and receive sides of the UART both have the equivalent of a 1-byte holding register. You can manipulate flags to disable the FIFOs, allowing you to use the bottom entry of the FIFOs as a 1-byte register. However, this doesn't physically disable the FIFOs. When using the FIFOs as a 1-byte register, a write to the data register bypasses the holding register unless the transmit shift register is already in use.

12.1.3.2.6. System and diagnostic loopback testing

To perform loopback testing for UART data, set the Loop Back Enable (LBE) bit to 1 in the Control Register, UARTCR . Data transmitted on UARTTXD is received on the UARTRXD input.

12.1.3.3. UART character frame

Figure 65. UART
character frame.

12.1.4. UART hardware flow control

The fully-selectable hardware flow control feature enables you to control the serial data flow with the nUARTRTS output and nUARTCTS input signals. Figure 66 shows how to communicate between two devices using hardware flow control:

Figure 66. Hardware
flow control between
two similar devices.

When the RTS flow control is enabled, nUARTRTS is asserted until the receive FIFO is filled up to the programmed watermark level. When the CTS flow control is enabled, the transmitter can only transmit data when nUARTCTS is asserted.

The hardware flow control is selectable using the RTSEn and CTSEn bits in the Control Register, UARTCR . Table 1026 shows how to configure UARTCR register bits to enable RTS and/or CTS.

Table 1026. Control bits to enable and disable hardware flow control.

NOTE

When RTS flow control is enabled, the software cannot use the RTSEn bit in the Control Register (UARTCR) to control the status of nUARTRTS.

12.1.4.1. RTS flow control

The RTS flow control logic is linked to the programmable receive FIFO watermark levels.

When RTS flow control is disabled, the receive FIFO receives data until full, or no more data is transmitted to it.

When RTS flow control is enabled, the nUARTRTS is asserted until the receive FIFO fills up to the watermark level. When the receive FIFO reaches the watermark level, the nUARTRTS signal is de-asserted. This indicates that the FIFO has no more room to receive data. The transmission of data is expected to cease after the current character has been transmitted. When the receive FIFO drains below the watermark level, the nUARTRTS signal is reasserted.

12.1.4.2. CTS flow control

The CTS flow control logic is linked to the nUARTCTS signal.

When CTS flow control is disabled, the transmitter transmits data until the transmit FIFO is empty.

When CTS flow control is enabled, the transmitter checks the nUARTCTS signal before transmitting each byte. It only transmits the byte if the nUARTCTS signal is asserted. As long as the transmit FIFO is not empty and nUARTCTS is asserted, data continues to transmit. If the transmit FIFO is empty and the nUARTCTS signal is asserted, no data is transmitted. If the nUARTCTS signal is de-asserted during transmission, the transmitter finishes transmitting the current character before stopping.

12.1.5. UART DMA interface

The UART provides an interface to connect to a DMA controller. The DMA operation of the UART is controlled using the DMA Control Register, UARTRDMACR. The DMA interface includes the following signals:

For receive:

UARTRXDMASREQ

Single character DMA transfer request, asserted by the UART. For receive, one character consists of up to 12 bits. This signal is asserted when the receive FIFO contains at least one character.

UARTRXDMABREQ

Burst DMA transfer request, asserted by the UART. This signal is asserted when the receive FIFO contains more characters than the programmed watermark level. You can program the watermark level for each FIFO using the Interrupt FIFO Level Select Register (UARTIFLS).

UARTEINTR . It enables the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ , to be masked out when the UART error interrupt, UARTEINTR , is asserted. The DMA receive request outputs remain inactive until the UARTEINTR is cleared. The DMA transmit request outputs are unaffected.

Figure 67. DMA transfer waveforms.

Figure 67 shows the timing diagram for both a single transfer request and a burst transfer request with the appropriate DMACLR signal. The signals are all synchronous to PCLK. For the sake of clarity it is assumed that there is no synchronization of the request signals in the DMA controller.

12.1.6. Interrupts

There are eleven maskable interrupts generated in the UART. On RP2350, only the combined interrupt output, UARTINTR , is connected.

To enable or disable individual interrupts, change the mask bits in the Interrupt Mask Set/Clear Register, UARTIMSC . Set the appropriate mask bit HIGH to enable the interrupt.

The transmit and receive dataflow interrupts UARTRXINTR and UARTTXINTR have been separated from the status interrupts. This enables you to use UARTRXINTR and UARTTXINTR to read or write data in response to FIFO trigger levels.

The error interrupt, UARTEINTR , can be triggered when there is an error in the reception of data. A number of error conditions are possible.

The modem status interrupt, UARTMSINTR , is a combined interrupt of all the individual modem status signals.

The status of the individual interrupt sources can be read either from the Raw Interrupt Status Register, UARTRIS , or from the Masked Interrupt Status Register, UARTMIS .

12.1.6.1. UARTMSINTR

The modem status interrupt is asserted if any of the modem status signals ( nUARTCTS , nUARTDCD , nUARTDSR , and nUARTRI ) change. To clear the modem status interrupt, write a 1 to the bits corresponding to the modem status signals that generated the interrupt in the Interrupt Clear Register ( UARTICR ).

12.1.6.2. UARTRXINTR

The receive interrupt changes state when one of the following events occurs:

• • The FIFOs are enabled and the receive FIFO reaches the programmed trigger level. This asserts the receive interrupt HIGH. To clear the receive interrupt, read data from the receive FIFO until it drops below the trigger level.
• • The FIFOs are disabled (have a depth of one location) and data is received, thereby filling the receive FIFO. This asserts the receive interrupt HIGH. To clear the receive interrupt, perform a single read from the receive FIFO.

In both cases, you can also clear the interrupt manually.

12.1.6.3. UARTTXINTR

The transmit interrupt changes state when one of the following events occurs:

• • The FIFOs are enabled and the transmit FIFO is equal to or lower than the programmed trigger level. This asserts the transmit interrupt HIGH. To clear the transmit interrupt, write data to the transmit FIFO until it exceeds the

trigger level.

• • The FIFOs are disabled (have a depth of one location) and there is no data present in the transmit FIFO. This asserts the transmit interrupt HIGH. To clear the transmit interrupt, perform a single write to the transmit FIFO.

In both cases, you can also clear the interrupt manually.

To update the transmit FIFO, write data to the transmit FIFO before or after enabling the UART and the interrupts.

i NOTE

The transmit interrupt is based on a transition through a level, rather than on the level itself. When the interrupt and the UART is enabled before any data is written to the transmit FIFO, the interrupt is not set. The interrupt is only set after written data leaves the single location of the transmit FIFO and it becomes empty.

12.1.6.4. UARTRINTR

The receive timeout interrupt is asserted when the receive FIFO is not empty and no more data is received during a 32-bit period.

The receive timeout interrupt is cleared in the following scenarios:

• • the FIFO becomes empty through reading all the data or by reading the holding register
• • a 1 is written to the corresponding bit of the Interrupt Clear Register, UARTICR

12.1.6.5. UARTEINTR

The error interrupt is asserted when an error occurs in the reception of data by the UART. The interrupt can be caused by a number of different error conditions:

• • framing
• • parity
• • break
• • overrun

To determine the cause of the interrupt, read the Raw Interrupt Status Register ( UARTISR ) or the Masked Interrupt Status Register ( UARTMIS ). To clear the interrupt, write to the relevant bits of the Interrupt Clear Register, UARTICR (bits 7 to 10 are the error clear bits).

12.1.6.6. UARTINTR

The interrupts are also combined into a single output, that is an OR function of the individual masked sources. You can connect this output to a system interrupt controller to provide another level of masking on a individual peripheral basis.

The combined UART interrupt is asserted if any of the individual interrupts are asserted and enabled.

12.1.7. Programmer's model

The SDK provides a uart_init function to configure the UART with a particular baud rate. Once the UART is initialised, the user must configure a GPIO pin as UART_TX and UART_RX . See Section 9.10.1 for more information on selecting a GPIO function.

To initialise the UART, the uart_init function takes the following steps:

1. 1. De-asserts the reset

1. 2. Enables clk_peri
2. 3. Sets enable bits in the control register
3. 4. Enables the FIFOs
4. 5. Sets the baud rate divisors
5. 6. Sets the format

SDK: https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_uart/uart.c Lines 42 - 92

42 uint uart_init(uart_inst_t *uart, uint baudrate) {
43     invalid_params_if(HARDWARE_UART, uart != uart0 && uart != uart1);
44
45     if (uart_clock_get_hz(uart) == 0) {
46         return 0;
47     }
48
49     uart_reset(uart);
50     uart_unreset(uart);
51
52     uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF);
53
54     // Any LCR writes need to take place before enabling the UART
55     uint baud = uart_set_baudrate(uart, baudrate);
56
57     // inline the uart_set_format() call, as we don't need the CR disable/re-enable
58     // protection, and also many people will never call it again, so having
59     // the generic function is not useful, and much bigger than this inlined
60     // code which is only a handful of instructions.
61     //
62     // The UART_UARTLCR_H_FEN_BITS setting is combined as well as it is the same register
63     #ifdef 0
64         uart_set_format(uart, 8, 1, UART_PARITY_NONE);
65         // Enable FIFOs (must be before setting UARTEN, as this is an LCR access)
66         hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
67     #else
68         uint data_bits = 8;
69         uint stop_bits = 1;
70         uint parity = UART_PARITY_NONE;
71         hw_write_masked(&uart_get_hw(uart)->lcr_h,
72             (((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) |
73              ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) |
74              (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) |
75              (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB) |
76              UART_UARTLCR_H_FEN_BITS,
77              UART_UARTLCR_H_WLEN_BITS | UART_UARTLCR_H_STP2_BITS |
78              UART_UARTLCR_H_PEN_BITS | UART_UARTLCR_H_EPS_BITS |
79              UART_UARTLCR_H_FEN_BITS);
80     #endif
81
82     // Enable the UART, both TX and RX
83     uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS |
        UART_UARTCR_RXE_BITS;
84     // Always enable DREQ signals -- no harm in this if DMA is not listening
85     uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
86
87     return baud;
88 }

12.1.7.1. Baud rate calculation

The UART baud rate is derived from dividing clk_peri .

If the required baud rate is 115200 and UARTCLK = 125MHz then:

Baud Rate Divisor = \( (125 \times 10^6)/(16 \times 115200) \sim 67.817 \)

Therefore, BRDI = 67 and BRDF = 0.817,

Therefore, fractional part, m = integer((0.817 × 64) + 0.5) = 52

Generated baud rate divider = 67 + 52/64 = 67.8125

Generated baud rate = \( (125 \times 10^6)/(16 \times 67.8125) \sim 115207 \)

Error = \( (\text{abs}(115200 - 115207) / 115200) \times 100 \sim 0.006\% \)

SDK: https://github.com/raspberrypi/pico-sdk/blob/master/src/rp2_common/hardware_uart/uart.c Lines 155 - 180

155 uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
156     invalid_params_if(HARDWARE_UART, baudrate == 0);
157     uint32_t baud_rate_div = (8 * uart_clock_get_hz(uart) / baudrate) + 1;
158     uint32_t baud_ibrd = baud_rate_div >> 7;
159     uint32_t baud_fbrd;
160
161     if (baud_ibrd == 0) {
162         baud_ibrd = 1;
163         baud_fbrd = 0;
164     } else if (baud_ibrd >= 65535) {
165         baud_ibrd = 65535;
166         baud_fbrd = 0;
167     } else {
168         baud_fbrd = (baud_rate_div & 0x7f) >> 1;
169     }
170
171     uart_get_hw(uart)->ibrd = baud_ibrd;
172     uart_get_hw(uart)->fbrd = baud_fbrd;
173
174     // PL011 needs a (dummy) LCR_H write to latch in the divisors.
175     // We don't want to actually change LCR_H contents here.
176     uart_write_lcr_bits_masked(uart, 0, 0);
177
178     // See datasheet
179     return (4 * uart_clock_get_hz(uart)) / (64 * baud_ibrd + baud_fbrd);
180 }

12.1.8. List of registers

The UART0 and UART1 registers start at base addresses of 0x40070000 and 0x40078000 respectively (defined as UART0_BASE and UART1_BASE in SDK).

Table 1028. List of UART registers

UART: UARTDR Register

Offset: 0x000

Description

Data Register, UARTDR

Table 1029. UARTDR Register

UART: UARTRSR Register

Offset: 0x004

Description

Receive Status Register/Error Clear Register, UARTRSR/UARTECR

Table 1030. UARTRSR Register

UART: UARTFR Register

Offset: 0x018

Description

Flag Register, UARTFR

Table 1031. UARTFR Register

UART: UARTILPR Register

Offset: 0x020

Description

IrDA Low-Power Counter Register, UARTILPR

Table 1032. UARTILPR Register

UART: UARTIBRD Register

Offset: 0x024

Description

Integer Baud Rate Register, UARTIBRD

Table 1033. UARTIBRD Register

UART: UARTFBRD Register

Offset: 0x028

Description

Fractional Baud Rate Register, UARTFBRD

Table 1034.
UARTFBRD Register

UART: UARTLCR_H Register

Offset: 0x02c

Description

Line Control Register, UARTLCR_H

Table 1035.
UARTLCR_H Register

UART: UARTCR Register

Offset: 0x030

Control Register, UARTCR

Table 1036. UARTCR Register

UART: UARTIFLS Register

Offset: 0x034

Description

Interrupt FIFO Level Select Register, UARTIFLS

Table 1037. UARTIFLS Register

UART: UARTIMSC Register

Offset: 0x038

Description

Interrupt Mask Set/Clear Register, UARTIMSC

Table 1038. UARTIMSC Register

UART: UARTRIS Register

Offset: 0x03c

Description

Raw Interrupt Status Register, UARTRIS

Table 1039. UARTRIS Register

UART: UARTMIS Register

Offset: 0x040

Description

Masked Interrupt Status Register, UARTMIS

Table 1040. UARTMIS Register

UART: UARTICR Register

Offset: 0x044

Description

Interrupt Clear Register, UARTICR

Table 1041. UARTICR Register

UART: UARTDMACR Register

Offset: 0x048

Description

DMA Control Register, UARTDMACR

Table 1042. UARTDMACR Register

UART: UARTPERIPHID0 Register

Offset: 0xfe0

Description

UARTPeriphID0 Register

Table 1043.
UARTPERIPHID0
Register

UART: UARTPERIPHID1 Register

Offset: 0xfe4

Description

UARTPeriphID1 Register

Table 1044.
UARTPERIPHID1
Register

UART: UARTPERIPHID2 Register

Offset: 0xfe8

Description

UARTPeriphID2 Register

Table 1045.
UARTPERIPHID2
Register

UART: UARTPERIPHID3 Register

Offset: 0xfec

Description

UARTPeriphID3 Register

Table 1046.
UARTPERIPHID3
Register

UART: UARTPCELLID0 Register

Offset: 0xff0

Description

UARTPCellID0 Register

Table 1047.
UARTPCELLID0
Register

UART: UARTPCELLID1 Register

Offset: 0xff4

Description

UARTPCellID1 Register

Table 1048.
UARTPCELLID1
Register

UART: UARTPCELLID2 Register

Offset: 0xff8

Description

UARTPCellID2 Register

Table 1049.
UARTPCELLID2
Register

UART: UARTPCELLID3 Register

Offset: 0xffc

Description

UARTPCellID3 Register

Table 1050.
UARTPCELLID3
Register

12.2. I2C

Synopsys Documentation

Synopsys Proprietary. Used with permission.

I2C is a commonly used 2-wire interface that can be used to connect devices for low speed data transfer using clock SCL and data SDA wires.

RP2350 has two identical instances of an I2C controller. The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in Section 9.4 . The muxing options give some IO flexibility.

12.2.1. Features

Each I2C controller is based on a configuration of the Synopsys DW_apb_i2c (v2.03a) IP. The following features are supported:

• • Master or Slave (Default to Master mode)
• • Standard mode, Fast mode or Fast mode plus
• • Default slave address 0x055
• • Supports 10-bit addressing in Master mode
• • 16-element transmit buffer
• • 16-element receive buffer
• • Can be driven from DMA
• • Can generate interrupts

12.2.1.1. Standard

The I2C controller was designed for I2C Bus specification, version 6.0, dated April 2014.

12.2.1.2. Clocking

All clocks in the I2C controller are connected to clk_sys , including ic_clk , which is mentioned in later sections. The I2C clock is generated by dividing down this clock, controlled by registers inside the block.

12.2.1.3. IOs

Each controller must connect its clock SCL and data SDA to one pair of GPIOs. The I2C standard requires that drivers drive a signal low, or when not driven the signal will be pulled high. This applies to SCL and SDA. The GPIO pads should be configured for:

• • pull-up enabled
• • slew rate limited
• • schmitt trigger enabled

NOTE

There should also be external pull-ups on the board as the internal pad pull-ups may not be strong enough to pull up external circuits.

12.2.2. IP configuration

I2C configuration details (each instance is fully independent):

• • 32-bit APB access
• • Supports Standard mode, Fast mode or Fast mode plus (not High speed)
• • Default slave address of 0x055
• • Master or Slave mode
• • Master by default (Slave mode disabled at reset)

• • 10-bit addressing supported in master mode (7-bit by default)
• • 16 entry transmit buffer
• • 16 entry receive buffer
• • Allows restart conditions when a master (can be disabled for legacy device support)
• • Configurable timing to adjust \( T_{suDAT}/T_{hDAT} \)
• • General calls responded to on reset
• • Interface to DMA
• • Single interrupt output
• • Configurable timing to adjust clock frequency
• • Spike suppression (default 7 \( clk_{sys} \) cycles)
• • Can NACK after data received by Slave
• • Hold transfer when TX FIFO empty
• • Hold bus until space available in RX FIFO
• • Restart detect interrupt in Slave mode
• • Optional blocking Master commands (not enabled by default)

12.2.3. I2C overview

The I2C bus is a 2-wire serial interface, consisting of a serial data line SDA and a serial clock SCL . These wires carry information between the devices connected to the bus. Each device is recognized by a unique address and can operate as either a "transmitter" or "receiver", depending on the function of the device. Devices can also be considered as masters or slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

i NOTE

The I2C block must only be programmed to operate in either master OR slave mode only. Operating as a master and slave simultaneously is not supported.

The I2C block can operate in these modes:

• • standard mode (with data rates from 0 to 100 kb/s),
• • fast mode (with data rates up to 400 kb/s),
• • fast mode plus (with data rates up to 1000 kb/s).

These modes are not supported:

• • High-speed mode (with data rates up to 3.4Mb/s),
• • Ultra-Fast Speed Mode (with data rates up to 5Mb/s).

i NOTE

References to fast mode also apply to fast mode plus, unless specifically stated otherwise.

The I2C block can communicate with devices in one of these modes as long as they are attached to the bus. Additionally, fast mode devices are downward compatible. For instance, fast mode devices can communicate with standard mode devices at up to 100 kb/s over the I2C bus system. However, standard mode devices are not upward compatible and should not be incorporated in a fast-mode I2C bus system as they cannot follow the higher transfer rate; unpredictable states would occur.

The following devices commonly use high-speed mode:

• • LCD displays
• • high-bit count ADCs
• • high capacity EEPROMs

These devices typically need to transfer large amounts of data.

Most maintenance and control applications, the common use for the I2C bus, typically operate at 100 kHz in standard and fast modes. Any DW_apb_i2c device can be attached to an I2C bus. Every device can talk with any master, passing information back and forth. There needs to be at least one master (such as a microcontroller or DSP) on the bus, but there can be multiple masters, which require them to arbitrate for ownership. Multiple masters and arbitration are explained later in this chapter. The I2C block does not support SMBus and PMBus protocols (for System management and Power management).

The DW_apb_i2c is made up of:

• • an AMBA APB slave interface
• • an I2C interface
• • FIFO logic to maintain coherency between the two interfaces

The blocks of the component are illustrated in Figure 68 .

Figure 68. I2C Block diagram

The following define the functions of the blocks in Figure 68 :

• • AMBA Bus Interface Unit: Takes the APB interface signals and translates them into a common generic interface that allows the register file to be bus protocol-agnostic.
• • Register File: Contains configuration registers and is the interface with software.
• • Slave State Machine: Follows the protocol for a slave and monitors bus for address match.
• • Master State Machine: Generates the I2C protocol for the master transfers.
• • Clock Generator: Calculates the required timing to do the following:
  • ◦ Generate the SCL clock when configured as a master
  • ◦ Check for bus idle
  • ◦ Generate a START and a STOP
  • ◦ Setup the data and hold the data
• • RX Shift: Takes data into the design and extracts it in byte format.

• • TX Shift: Presents data supplied by CPU for transfer on the I2C bus.
• • RX Filter: Detects the events in the bus; for example, start, stop and arbitration lost.
• • Toggle: Generates pulses on both sides and toggles to transfer signals across clock domains.
• • Synchronizer: Transfers signals from one clock domain to another.
• • DMA Interface: Generates the handshaking signals to the central DMA controller in order to automate the data transfer without CPU intervention.
• • Interrupt Controller: Generates the raw interrupt and interrupt flags, allowing them to be set and cleared.
• • RX FIFO/TX FIFO: Holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels.

12.2.4. I2C terminology

This section defines key terms used in various parts of the I2C.

12.2.4.1. I2C bus terms

The following terms relate to how the role of the I2C device and how it interacts with other I2C devices on the bus.

Transmitter

the device that sends data to the bus. A transmitter can either be a device that initiates the data transmission to the bus (a master-transmitter) or the device that responds to a request from the master to send data to the bus (a slave-transmitter).

Receiver

the device that receives data from the bus. A receiver can either be a device that receives data on its own request (a master-receiver) or a device that receives data in response to a request from the master (a slave-receiver).

Master

the component that initializes a transfer (START command), generates the clock SCL signal and terminates the transfer (STOP command). A master can be either a transmitter or a receiver.

Slave

the device addressed by the master. A slave can be either receiver or transmitter.

Multi-master

the ability for more than one master to co-exist on the bus at the same time without collision or data loss.

Arbitration

the predefined procedure that authorizes only one master at a time to take control of the bus. For more information about this behaviour, refer to Section 12.2.8 .

Synchronization

the predefined procedure that synchronizes the clock signals provided by two or more masters. For more information about this feature, refer to Section 12.2.9 .

SDA

the data signal line (Serial Data).

SCL

the clock signal line (Serial Clock).

12.2.4.2. Bus transfer terms

The following terms are specific to data transfers that occur to and from the I2C bus.

START (RESTART)

data transfer begins with a START or RESTART condition. The level of the SDA data line changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomes busy.

NOTE

START and RESTART conditions are functionally identical.

STOP

data transfer is terminated by a STOP condition. This occurs when the level on the SDA data line passes from the low state to the high state, while the SCL clock line remains high. When the data transfer has been terminated, the bus is free or idle once again. The bus stays busy if a RESTART is generated instead of a STOP condition.

12.2.5. I2C behaviour

The DW_apb_i2c can be controlled with software to be one of the following:

• • An I2C master only, communicating with other I2C slaves
• • An I2C slave only, communicating with one or more I2C masters.

The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible for either transmitting or receiving data to and from the master. The acknowledgement of data is sent by the device that is receiving data, which can be either a master or a slave. As mentioned previously, the I2C protocol also allows multiple masters to reside on the I2C bus and uses an arbitration procedure to determine bus ownership.

Each slave has a unique address determined by the system designer. When a master wants to communicate with a slave:

1. 1. The master transmits a START/RESTART condition that is then followed by the slave’s address and a control bit (R/W) to determine if the master wants to transmit data or receive data from the slave.
2. 2. The slave then sends an acknowledge (ACK) pulse after the address.

When the master (master-transmitter) writes to the slave (slave-receiver), the receiver gets one byte of data. This transaction continues until the master terminates the transmission with a STOP condition.

When the master reads from a slave (master-receiver), the slave transmits (slave-transmitter) a byte of data to the master. The master then acknowledges the transaction with the ACK pulse. This transaction continues until the master terminates the transmission by not acknowledging (NACK) the transaction after the last byte is received, and then the master issues a STOP condition or addresses another slave after issuing a RESTART condition. This behaviour is illustrated in Figure 69.

Figure 69. Data transfer on the I2C Bus

The DW_apb_i2c is a synchronous serial interface. The SDA line is a bidirectional signal that changes only while the SCL line is low except for STOP, START, and RESTART conditions. The output drivers are open-drain or open-collector to perform wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum capacitance specification of 400 pF. Data is transmitted in byte packages.

The I2C protocols implemented in DW_apb_i2c are described in more details in Section 12.2.6.

12.2.5.1. START and STOP generation

When operating as an I2C master, putting data into the TX FIFO causes the DW_apb_i2c to generate a START condition on the I2C bus. Writing a 1 to IC_DATA_CMD.STOP causes the DW_apb_i2c to generate a STOP condition on the I2C bus; a STOP condition is not issued if this bit is not set, even if the TX FIFO is empty.

When operating as a slave, the DW_apb_i2c does not generate START and STOP conditions, as per the protocol. However, if a read request is made to the DW_apb_i2c , it holds the SCL line low until read data has been supplied to it. This stalls the I2C bus until read data is provided to the slave DW_apb_i2c , or the DW_apb_i2c slave is disabled by writing a 0 to IC_ENABLE.ENABLE .

12.2.5.2. Combined formats

The DW_apb_i2c supports mixed read and write combined format transactions in both 7-bit and 10-bit addressing modes. The DW_apb_i2c does not support mixed address and mixed address format - that is, a 7-bit address transaction followed by a 10-bit address transaction or vice versa-combined format transactions. To initiate combined format transfers, IC_CON.IC_RESTART_EN should be set to 1. With this value set and operating as a master, when the DW_apb_i2c completes an I2C transfer, it checks the TX FIFO and executes the next transfer. If the direction of this transfer differs from the previous transfer, the combined format is used to issue the transfer. If the TX FIFO is empty when the current I2C transfer completes:

• • IC_DATA_CMD.STOP is checked and:
  • ◦ If set to 1, a STOP bit is issued.
  • ◦ If set to 0, the SCL is held low until the next command is written to the TX FIFO.

For more details, refer to Section 12.2.7 .

12.2.6. I2C protocols

This section defines protocols used in the DW_apb_i2c .

12.2.6.1. START and STOP conditions

When the bus is idle, both the SCL and SDA signals are pulled high through external pull-up resistors on the bus. When the master wants to start a transmission on the bus, the master issues a START condition : a high-to-low transition of the SDA signal while SCL is 1. When the master wants to terminate the transmission, the master issues a STOP condition : a low-to-high transition of the SDA signal while SCL is 1. Figure 70 shows the timing of the START and STOP conditions. When data is being transmitted on the bus, the SDA signal must be stable when SCL is set to 1.

Figure 70. I2C START and STOP Condition

NOTE

The signal transitions for the START/STOP conditions, as depicted in Figure 70 , reflect those observed at the output signals of the master driving the I2C bus. Care should be taken when observing the SDA/SCL signals at the input signals of slaves, because unequal line delays may result in an incorrect SDA/SCL timing relationship.

12.2.6.2. Addressing slave protocol

There are two address formats: 7-bit and 10-bit.

12.2.6.2.1. 7-bit address format

In the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the LSB bit (bit 0) defines the R/W status, as shown in Figure 71 . When bit 0 is set to 0, the master writes to the slave. When bit 0 is set to 1, the master reads from the slave.

Figure 71. I2C 7-bit Address Format

12.2.6.2.2. 10-bit address format

The 10-bit address format transfers two bytes for each 10-bit address.

• • In the first byte, the first five bits (bits 7:3) indicate a 10-bit transfer. The next two bits (bits 2:1) contain bits 9:8 of the slave address. The LSB bit (bit 0) defines the R/W status.
• • The second byte contains bits 7:0 of the slave address.

Figure 72 shows the 10-bit address format:

Figure 72. 10-bit Address Format

This table defines the special purpose and reserved first byte addresses.

Table 1051.
I2C/SMBus Definition
of Bits in First Byte

DW_apb_i2c does not restrict you from using reserved addresses. However, if you use these reserved addresses, you may experience incompatibilities with I2C components.

12.2.6.3. Transmitting and receiving protocol

The master can initiate data transmission and reception to and from the bus, acting as either a master-transmitter or master-receiver. A slave responds to requests from the master to either transmit data or receive data to/from the bus, acting as either a slave-transmitter or slave-receiver, respectively.

12.2.6.3.1. Master-transmitter and slave-receiver

All data is transmitted in byte format, with no limit on the number of bytes transferred per data transfer. After the master sends the address and R/W bit or the master transmits a byte of data to the slave, the slave-receiver must respond with the acknowledge signal (ACK). When no slave-receiver responds with an ACK pulse, the master aborts the transfer by issuing a STOP condition. The slave must leave the SDA line high so that the master can abort the transfer. If the master-transmitter is transmitting data as shown in Figure 73 , the slave-receiver responds to the master-transmitter with an acknowledge pulse after every byte of data is received.

Figure 73. I2C Master-Transmitter Protocol

12.2.6.3.2. Master-receiver and slave-transmitter

If the master is receiving data as shown in Figure 74 the master responds to the slave-transmitter with an acknowledge pulse after receiving each byte of data, except for the last byte. This is the way the master-receiver notifies the slave-transmitter that this is the last byte. The slave-transmitter relinquishes the SDA line after detecting No Acknowledge (NACK) so that the master can issue a STOP condition.

Figure 74. I2C Master-Receiver Protocol

When a master does not want to relinquish the bus with a STOP condition, the master can issue a RESTART condition. This is identical to a START condition except it occurs after the ACK pulse. Operating in master mode, the DW_apb_i2c can then communicate with the same slave using a transfer of a different direction. For a description of the combined format transactions that the DW_apb_i2c supports, see Section 12.2.5.2 .

NOTE

The DW_apb_i2c must be completely disabled before the target slave address register ( IC_TAR ) can be reprogrammed.

12.2.6.4. START BYTE Transfer Protocol

The START BYTE transfer protocol is designed for systems that do not have an on-board dedicated I2C hardware module. When the DW_apb_i2c is addressed as a slave, it always samples the I2C bus at the highest speed supported so that it never requires a START BYTE transfer. However, when DW_apb_i2c is a master, it supports the generation of START BYTE transfers at the beginning of every transfer in case a slave device requires it.

This protocol consists of the transmission of seven zeros, followed by a one, as illustrated in Figure 75 . This allows the processor polling the bus to under-sample the address phase until zero is detected. Once the microcontroller detects a zero, it switches from the under sampling rate to the correct rate of the master.

Figure 75. I2C Start Byte Transfer

The START BYTE procedure is as follows:

1. 1. Master generates a START condition.
2. 2. Master transmits the START byte (0000 0001).
3. 3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on the bus)
4. 4. No slave sets the ACK signal to zero.
5. 5. Master generates a RESTART (R) condition.

Hardware receivers do not respond to the START BYTE procedure because it uses a reserved address and resets after the RESTART condition generates.

12.2.7. TX FIFO Management and START, STOP and RESTART Generation

When operating as a master, the DW_apb_i2c component supports the mode of TX (transmit) FIFO management illustrated in Figure 76.

12.2.7.1. TX FIFO management

The component does not generate a STOP if the TX FIFO becomes empty; in this situation the component holds the SCL line low, stalling the bus until a new entry is available in the TX FIFO. A STOP condition is generated only when the user specifically requests it by setting bit nine (Stop bit) of the command written to IC_DATA_CMD register. Figure 76 shows the bits in the IC_DATA_CMD register.

Figure 76.
IC_DATA_CMD
Register

Figure 77 illustrates the behaviour of the DW_apb_i2c when the TX FIFO becomes empty while operating as a master transmitter, as well as the generation of a STOP condition.

Figure 77. Master
Transmitter - TX FIFO
Empties/STOP
Generation

Figure 78 illustrates the behaviour of the DW_apb_i2c when the TX FIFO becomes empty while operating as a master receiver, as well as the generation of a STOP condition.

Figure 78. Master
Receiver - TX FIFO
Empties/STOP
Generation

Figure 79 and Figure 80 illustrate configurations where the user can control the generation of RESTART conditions on the I2C bus. If bit 10 (Restart) of the IC_DATA_CMD register is set and the restart capability is enabled ( IC_RESTART_EN=1 ), a RESTART is generated before the data byte is written to or read from the slave. If the restart capability is not enabled, a STOP followed by a START is generated in place of the RESTART. Figure 79 illustrates this situation during operation as a master transmitter.

Figure 79. Master Transmitter - Restart Bit of IC_DATA_CMD Is Set

Figure 84. Master Receiver - First Command Loaded After TX FIFO Allowed to Empty/Restart Bit Set

12.2.8. Multiple master arbitration

The DW_apb_i2c bus protocol allows multiple masters to reside on the same bus. If there are two masters on the same I2C bus, there is an arbitration procedure if both try to take control of the bus at the same time by generating a START condition at the same time. Once a master (for example, a microcontroller) has control of the bus, no other master can take control until the first master sends a STOP condition and places the bus in an idle state.

Arbitration takes place on the SDA line, while the SCL line is set to 1. The master, which transmits a one while the other master transmits zero, loses arbitration and turns off its data output stage. The master that lost arbitration can continue to generate clocks until the end of the byte transfer. If both masters address the same slave device, the arbitration could go into the data phase.

Upon detecting that it has lost arbitration to another master, the DW_apb_i2c stops generating SCL by disabling the output driver. Figure 85 illustrates the timing of two masters arbitrating on the bus.

Figure 85. Multiple Master Arbitration

Control of the bus is determined by address or master code and data sent by competing masters, so there is no central master nor any order of priority on the bus.

Arbitration is not allowed between the following conditions:

• • A RESTART condition and a data bit
• • A STOP condition and a data bit
• • A RESTART condition and a STOP condition

i NOTE

Slaves do not participate in the arbitration process.

12.2.9. Clock synchronisation

When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize the SCL clock. All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL .

clock. Clock synchronisation is performed using the wired-AND connection to the SCL signal. When the master transitions the SCL clock to zero, the master starts counting the low time of the SCL clock and transitions the SCL clock signal to one at the beginning of the next clock period. However, if another master is holding the SCL line to 0, then the master goes into a HIGH wait state until the SCL clock line transitions to one.

All masters then count off their high time, and the master with the shortest high time transitions the SCL line to zero. The masters then count out their low time and the one with the longest low time forces the other masters into a HIGH wait state. Therefore, a synchronized SCL clock is generated, which is illustrated in Figure 86. Optionally, slaves may hold the SCL line low to slow down the timing on the I2C bus.

Figure 86. Multi-Master Clock Synchronisation

12.2.10. Operation modes

This section provides information about operation modes.

i NOTE

Only set the DW_apb_i2c to operate as an I2C Master or an I2C Slave. Never set the DW_apb_i2c to operate as both simultaneously. To avoid this, never simultaneously set IC_CON.IC_SLAVE_DISABLE and IC_CON.MASTER_MODE to zero and one, respectively.

12.2.10.1. Slave mode operation

This section discusses slave mode procedures.

12.2.10.1.1. Initial configuration

To use the DW_apb_i2c as a slave, perform the following steps:

1. 1. Disable the DW_apb_i2c by writing a 0 to IC_ENABLE.ENABLE .
2. 2. Write to the IC_SAR register (bits 9:0) to set the slave address. This is the address to which the DW_apb_i2c responds.
3. 3. Write to the IC_CON register to specify which type of addressing is supported (7-bit or 10-bit by setting bit 3). Enable the DW_apb_i2c in slave-only mode by writing a 0 into bit six ( IC_CON.IC_SLAVE_DISABLE ) and a 0 to bit zero ( IC_CON.MASTER_MODE ).

Slaves and masters can use different addressing settings. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit addressing, and vice versa.

1. 4. Enable the DW_apb_i2c by writing a 1 to IC_ENABLE.ENABLE .

Depending on the reset values chosen, steps two and three may not be necessary because the reset values can be configured. For instance, if the device is only going to be a master, there would be no need to set the slave address because you can configure DW_apb_i2c to have the slave disabled after reset and to enable the master after reset. The values stored are static and do not need to be reprogrammed if the DW_apb_i2c is disabled.

Only bring the DW_apb_i2c Slave out of reset when the I2C bus is IDLE. De-asserting the reset when a transfer is ongoing on the bus causes internal synchronization flip-flops used to synchronize SDA and SCL to toggle from a reset value of one to the actual value on the bus. This can result in SDA toggling from one to zero while SCL is one, thereby causing a false START condition to be detected by the DW_apb_i2c Slave. This scenario can also be avoided by configuring the DW_apb_i2c with IC_SLAVE_DISABLE = 1 and MASTER_MODE = 1 so that the Slave interface is disabled after reset. It can then be enabled by programming IC_CON[0] = 0 and IC_CON[6] = 0 after the internal SDA and SCL have synchronized to the value on the bus; this takes approximately six ic_clk cycles after reset de-assertion.

When another I2C master device on the bus addresses the DW_apb_i2c and requests data, the DW_apb_i2c acts as a slave-transmitter. The following steps occur:

1. 1. The other I2C master device initiates an I2C transfer with an address that matches the slave address in the IC_SAR register of the DW_apb_i2c .
2. 2. The DW_apb_i2c acknowledges the sent address and recognizes the direction of the transfer to indicate that it is acting as a slave-transmitter.
3. 3. The DW_apb_i2c asserts the RD_REQ interrupt (bit five of the IC_RAW_INTR_STAT register) and holds the SCL line low. It remains in a wait state until software responds. If the RD_REQ interrupt has been masked, due to IC_INTR_MASK.M_RD_REQ being set to zero, use a hardware and/or software timing routine to instruct the CPU to perform periodic reads of the IC_RAW_INTR_STAT register.
   • ◦ Reads that indicate IC_RAW_INTR_STAT.RD_REQ being set to one must be treated as the equivalent of the RD_REQ interrupt being asserted.
   • ◦ Software must then act to satisfy the I2C transfer.
   • ◦ The timing interval used should be in the order of 10 times the fastest SCL clock period the DW_apb_i2c can handle. For example, for 400 kb/s, the timing interval is 25µs.

The value of 10 is recommended here because this is approximately the amount of time required for a single byte of data transferred on the I2C bus.

1. 4. If there is any data remaining in the TX FIFO before receiving the read request, the DW_apb_i2c asserts a TX_ABRT interrupt (bit six of the IC_RAW_INTR_STAT register) to flush the old data from the TX FIFO. If the TX_ABRT interrupt has been masked, due to IC_INTR_MASK.M_TX_ABRT being set to zero, re-use the timing routine described in the previous step to read the IC_RAW_INTR_STAT register.

Because the DW_apb_i2c 's TX FIFO is forced into a flushed/reset state whenever a TX_ABORT event occurs, software must release the DW_apb_i2c from this state by reading the IC_CLR_TX_ABORT register before attempting to write into the TX FIFO. See register IC_RAW_INTR_STAT for more details.

1. • ◦ Reads that indicate bit six ( R_TX_ABORT ) being set to one must be treated as the equivalent of the TX_ABORT interrupt being asserted.
   • ◦ There is no further action required from software.
   • ◦ The timing interval used should be similar to that described in the previous step for the IC_RAW_INTR_STAT.RD_REQ register.
2. 1. 5. Software writes to the IC_DATA_CMD register with the data to be written (by writing a 0 in bit 8).
   2. 6. Software must clear the RD_REQ and TX_ABORT interrupts (bits five and six, respectively) of the IC_RAW_INTR_STAT register before proceeding. If the RD_REQ or TX_ABORT interrupts have been masked, then clearing of the IC_RAW_INTR_STAT register will have already been performed when either the R_RD_REQ or R_TX_ABORT bit has been read as one.
   3. 7. The DW_apb_i2c releases the SCL and transmits the byte.
   4. 8. The master may hold the I2C bus by issuing a RESTART condition or release the bus by issuing a STOP condition.

Slave-Transmitter Operation for a single byte is not applicable in Ultra-Fast mode, since this mode does not support read transfers.

When another I2C master device on the bus addresses the DW_apb_i2c and is sending data, the DW_apb_i2c acts as a slave-receiver and the following steps occur:

1. 1. The other I2C master device initiates an I2C transfer with an address that matches the DW_apb_i2c 's slave address in the IC_SAR register.
2. 2. The DW_apb_i2c acknowledges the sent address and recognizes the direction of the transfer to indicate that the DW_apb_i2c is acting as a slave-receiver.
3. 3. DW_apb_i2c receives the transmitted byte and places it in the receive buffer.

If the Rx (receive) FIFO is completely filled with data when a byte is pushed, then the DW_apb_i2c slave holds the I2C SCL line low until the Rx FIFO has some space, and then continues with the next read request.

1. 4. DW_apb_i2c asserts the RX_FULL interrupt IC_RAW_INTR_STAT.RX_FULL . If the RX_FULL interrupt has been masked, due to setting IC_INTR_MASK.M_RX_FULL to zero or setting IC_TX_TL to a value larger than zero, you should implement a timing routine (described in Section 12.2.10.1.2) for periodic reads of the IC_STATUS register. This timing routine should treat reads of the IC_STATUS register, with bit 3 ( RFNE ) set at one as the equivalent of an RX_FULL interrupt.
2. 5. Software may read the byte from the IC_DATA_CMD register (bits 7:0).
3. 6. The other master device may hold the I2C bus by issuing a RESTART condition, or release the bus by issuing a STOP condition.

12.2.10.1.4. Slave-transfer operation for bulk transfers

In the standard I2C protocol, all transactions are single byte transactions; the programmer responds to a remote master read request by writing one byte into the slave's TX FIFO. When a slave (slave-transmitter) receives a read request ( RD_REQ ) from the remote master (master-receiver), at a minimum there should be at least one entry placed into the slave-transmitter's TX FIFO.

DW_apb_i2c handles more data in the TX FIFO. This enables subsequent read requests to take data without raising an interrupt. This eliminates latencies incurred between interrupts. This mode only occurs when DW_apb_i2c acts as a slave-transmitter. If the remote master acknowledges the data sent by the slave-transmitter and there is no data in the slave's TX FIFO, the DW_apb_i2c holds the I2C SCL line low while it raises the read request interrupt ( RD_REQ ) and waits for a data write into the TX FIFO.

If the RD_REQ interrupt is masked by setting IC_INTR_STAT.R_RD_REQ to zero, use a timing routine to activate periodic reads of the IC_RAW_INTR_STAT register. Reads of IC_RAW_INTR_STAT that return bit five ( RD_REQ ) set to one must be treated as the equivalent of RD_REQ . This timing routine is similar to that described in Section 12.2.10.1.2 .

The RD_REQ interrupt is raised upon a read request. Always clear this interrupt when exiting the interrupt service handling routine (ISR). The ISR allows you to either write one byte or more than one byte into the TX FIFO. The master can request additional data at the end of a transmission by acknowledging the last byte. In this scenario, the slave must raise RD_REQ again.

If you know in advance that the remote master requests a packet of n bytes, you can write n byte to the TX FIFO. Then, when another master addresses DW_apb_i2c and requests data, the remote master will receive a continuous stream of data. This happens because the DW_apb_i2c slave continues to send data to the remote master as long as the remote master acknowledges the data sent and there is data available in the TX FIFO. There is no need to hold the SCL line low or to issue RD_REQ again.

If the remote master doesn't read all of the bytes from the TX FIFO, the DW_apb_i2c ignores the excess bytes with the following procedure:

• • The DW_apb_i2c clears the TX FIFO.
• • The DW_apb_i2c generates a transmit abort ( TX_ABORT ) event.

At the time an ACK/NACK is expected, if a NACK is received, then the remote master has all the data it wants. At this time, a flag is raised within the slave's state machine to clear the leftover data in the TX FIFO. This flag is transferred to the processor bus clock domain where the FIFO exists and the contents of the TX FIFO is cleared at that time.

12.2.10.2. Master mode operation

This section discusses master mode procedures.

12.2.10.2.1. Initial configuration

To use the DW_apb_i2c as a master, perform the following steps:

1. 1. Disable the DW_apb_i2c by writing zero to IC_ENABLE.ENABLE .
2. 2. Write to the IC_CON register to set the maximum speed mode supported (bits 2:1) and the desired speed of the DW_apb_i2c master-initiated transfers, either 7-bit or 10-bit addressing (bit 4). Ensure that bit six ( IC_SLAVE_DISABLE ) is written with a 1 and bit zero ( MASTER_MODE ) is written with a 1.

Slaves and masters can use different addressing settings. For instance, a slave can be programmed with 7-bit addressing and a master with 10-bit addressing, and vice versa.

1. 3. Write the address of the I2C device to be addressed to bits 9:0 of the IC_TAR register. This register also determines whether the I2C will perform a General Call or a START BYTE command.
2. 4. Enable the DW_apb_i2c by writing a one to IC_ENABLE.ENABLE .
3. 5. Write the transfer direction and the data to be sent to the IC_DATA_CMD register. This step generates the START condition and the address byte on the DW_apb_i2c . Once DW_apb_i2c is enabled and there is data in the TX FIFO, DW_apb_i2c starts reading the data.

If you write to the IC_DATA_CMD register before enabling the DW_apb_i2c , the data and commands are lost: the buffers are kept cleared when DW_apb_i2c is disabled.

The values stored are static and do not need to be reprogrammed when the DW_apb_i2c is disabled except for transfer direction and data. As a result, you may not need to perform steps two, three, four, and five if you already configured the reset values.

The DW_apb_i2c supports switching back and forth between reading and writing dynamically. To transmit data, write data to the lower byte of the I2C RX/TX Data Buffer and Command Register ( IC_DATA_CMD ). For I2C write operations, write zero to the CMD bit [8]. Subsequently, to issue a read command, write a one to the CMD bit and write don't care to the lower byte of the IC_DATA_CMD register. The DW_apb_i2c master continues to initiate transfers as long as there are commands present in the TX FIFO. If the TX FIFO becomes empty, the master performs one of the following actions based on the value of IC_DATA_CMD :

• • If set to one, it issues a STOP condition after completing the current transfer.
• • If set to zero, it holds SCL low until next command is written to the TX FIFO.

For more details, refer to Section 12.2.7 .

The IC_ENABLE_STATUS register allows software to unambiguously determine when the I2C hardware has completely shut down.

Earlier versions of DW_apb_i2c required the programmer to monitor two registers: ( IC_STATUS and IC_RAW_INTR_STAT ). RP2350 only requires the programmer to monitor IC_ENABLE_STATUS .

To shut down I2C hardware, write a zero to IC_ENABLE.ENABLE . The DW_apb_i2c master can be disabled only if the command currently processing when the de-assertion occurs has the STOP bit set to one. If you attempt to disable the DW_apb_i2c master while processing a command without the STOP bit set, the DW_apb_i2c master continues to remain active, holding the SCL line low until a new command is received in the TX FIFO.

To relinquish the I2C bus and disable DW_apb_i2c while the DW_apb_i2c master is processing a command without the STOP bit set, issue an ABORT request .

12.2.10.3.1. Procedure

1. 1. Define a timer interval ( \( t_{i2c\_poll} \) ) equal to the 10 times the signalling period for the highest I2C transfer speed used in the system and supported by DW_apb_i2c . For example, if the highest I2C transfer mode is 400 kb/s, \( t_{i2c\_poll} \) is 25µs.
2. 2. Define a maximum time-out parameter, MAX_T_POLL_COUNT , such that if any repeated polling operation exceeds this maximum value, an error is reported.
3. 3. Execute a blocking thread, process, or function that prevents any further I2C master transactions from starting from software, but allows any pending transfers to be completed.

i NOTE

This step can be ignored if DW_apb_i2c is programmed to operate as an I2C slave only.

1. 1. The variable POLL_COUNT is initialized to zero.
2. 2. Set bit zero of the IC_ENABLE register to zero.
3. 3. Read the IC_ENABLE_STATUS register and test the IC_EN bit (bit 0). Increment POLL_COUNT by one. If POLL_COUNT >= MAX_T_POLL_COUNT , exit with the relevant error code.
4. 4. If IC_ENABLE_STATUS[0] is one, sleep for \( t_{i2c\_poll} \) and proceed to the previous step. Otherwise, exit with a relevant success code.

12.2.10.4. Aborting I2C transfers

The ABORT control bit of the IC_ENABLE register allows the software to relinquish the I2C bus before completing the issued transfer commands from the TX FIFO. In response to an ABORT request, the controller issues the STOP condition over the I2C bus, followed by a TX FIFO flush. Aborting the transfer is allowed only in master mode of operation.

12.2.10.4.1. Procedure

1. 1. Stop filling the TX FIFO ( IC_DATA_CMD ) with new commands.
2. 2. When operating in DMA mode, disable the transmit DMA by setting TDMAE to zero.
3. 3. Set IC_ENABLE.ABORT to one.
4. 4. Wait for the M_TX_ABRT interrupt.
5. 5. Read the IC_TX_ABRT_SOURCE register to identify the source as ABRT_USER_ABRT .

12.2.11. Spike suppression

The DW_apb_i2c contains programmable spike suppression logic that matches requirements imposed by the I2C Bus Specification for SS/FS modes. This logic is based on counters that monitor the input signals ( SCL and SDA ), checking if they remain stable for a predetermined amount of ic_clk cycles before they are sampled internally. There is one separate counter for each signal ( SCL and SDA ). The number of ic_clk cycles can be programmed by the user. The value should account for the frequency of ic_clk and the relevant spike length specification. Each counter starts whenever its input signal changes value. Depending on the behaviour of the input signal, one of the following scenarios occurs:

• • The input signal remains unchanged until the counter reaches its count limit value. When this happens, the counter resets and stops, and the internal version of the signal updates to the input value.
• • The input signal changes again before the counter reaches its count limit value. When this happens, the counter resets and stops, but the internal version of the signal does not update.

The timing diagram in Figure 87 illustrates the behaviour described above.

Figure 87. Spike
Suppression Example

NOTE

There is a 2-stage synchronizer on the SCL input. For the sake of simplicity, this synchronization delay was not included in the timing diagram in Figure 87 .

The I2C Bus Specification calls for different maximum spike lengths according to the operating mode (50 ns for SS and FS). Register IC_FS_SPKLEN holds the maximum spike length for SS and FS modes.

This register is 8 bits wide and accessible through the APB interface for reads and writes. However, you can only write to this register when the DW_apb_i2c is disabled. The minimum value that can be programmed into these registers is one; attempting to program a value smaller than one results in the value one being written.

The default value for these registers is based on the value of 100 ns for ic_clk period, so should be updated for the clk_sys period in use on RP2350.

NOTE

• • Because the minimum value that can be programmed into the IC_FS_SPKLEN register is one, the spike length specification can be exceeded for low frequencies of ic_clk . Consider the simple example of a 10 MHz (100 ns period) ic_clk ; in this case, the minimum spike length that can be programmed is 100 ns, which means that spikes up to this length are suppressed.
• • Standard synchronization logic (two flip-flops in series) is implemented upstream of the spike suppression logic and is not affected in any way by the contents of the spike length registers or the operation of the spike suppression logic; the two operations (synchronization and spike suppression) are completely independent. Because the SCL and SDA inputs are asynchronous to ic_clk , there is one ic_clk cycle uncertainty in the sampling of these signals. Depending on when they occur relative to the rising edge of ic_clk , spikes of the same original length might show a difference of one ic_clk cycle after being sampled.
• • Spike suppression is symmetrical; the behaviour is exactly the same for transitions from zero to one and from one to zero.

12.2.12. Fast mode plus operation

In fast mode plus, the DW_apb_i2c extends fast mode operation to be support speeds up to 1000 kb/s. To enable the DW_apb_i2c for fast mode plus operation, perform the following steps before initiating any data transfer:

1. 1. Set ic_clk frequency greater than or equal to 32 MHz (refer to Section 12.2.14.2.1 ).
2. 2. Program the IC_CON register [2:1] = 2'b10 for fast mode or fast mode plus.
3. 3. Program IC_FS_SCL_LCNT and IC_FS_SCL_HCNT registers to meet the fast mode plus SCL (refer to Section 12.2.14 ).
4. 4. Program the IC_FS_SPKLEN register to suppress the maximum spike of 50 ns.
5. 5. Program the IC_SDA_SETUP register to meet the minimum data setup time (tSU; DAT).

12.2.13. Bus clear feature

DW_apb_i2c supports the bus clear feature that provides graceful recovery of data SDA and clock SCL lines during unlikely events in which either the clock or data line is stuck at LOW.

12.2.13.1. SDA line is stuck at LOW

In case of SDA line stuck at LOW, the master performs the following actions to recover as shown in Figure 88 and Figure 89:

• 1. Master sends a maximum of nine clock pulses to recover the bus LOW within those nine clocks.
  • ◦ The number of clock pulses will vary with the number of bits that remain to be sent by the slave. As the maximum number of bits is nine, master sends up to nine clock pluses and allows the slave to recover.
  • ◦ The master attempts to assert a Logic 1 on the SDA line and check whether SDA is recovered. If the SDA is not recovered, it will continue to send a maximum of nine SCL clocks.
• 2. If SDA line is recovered within nine clock pulses, the master will send STOP to release the bus.
• 3. If SDA line is not recovered even after the ninth clock pulse, you must hardware reset the system.

Figure 88. SDA Recovery with 9 SCL Clocks

Figure 89. SDA Recovery with 6 SCL Clocks

12.2.13.2. SCL line is stuck at LOW

In the unlikely event (due to an electric failure of a circuit) where the clock (SCL) is stuck to LOW, there is no effective method to overcome this problem. Instead, reset the bus using the hardware reset signal.

12.2.14. IC_CLK frequency configuration

When the DW_apb_i2c is configured as a Standard (SS), Fast (FS), or Fast-Mode Plus (FM+), the *CNT registers must be set before any I2C bus transaction can take place in order to ensure proper I/O timing. The *CNT registers are:

• • IC_SS_SCL_HCNT
• • IC_SS_SCL_LCNT
• • IC_FS_SCL_HCNT
• • IC_FS_SCL_LCNT

NOTE

The tBUF timing and setup/hold time of START, STOP and RESTART registers uses *HCNT/*LCNT register settings for the corresponding speed mode.

It is not necessary to program any of the *CNT registers if the DW_apb_i2c is enabled to operate only as an I2C slave, since these registers are used only to determine the SCL timing requirements for operation as an I2C master.

Table 1052 lists the derivation of I2C timing parameters from the *CNT programming registers.

Table 1052. Derivation of I2C Timing Parameters from *CNT Registers

12.2.14.1. Minimum high and low counts in SS, FS, and FM+ modes.

When the DW_apb_i2c operates as an I2C master, in both transmit and receive transfers:

• • IC_SS_SCL_LCNT and IC_FS_SCL_LCNT register values must be larger than IC_FS_SPKLEN + 7.
• • IC_SS_SCL_HCNT and IC_FS_SCL_HCNT register values must be larger than IC_FS_SPKLEN + 5.

Details regarding the DW_apb_i2c high and low counts are as follows:

• • The minimum value of IC_*_SPKLEN + 7 for the *_LCNT registers is due to the time required for the DW_apb_i2c to drive SDA after a negative edge of SCL .
• • The minimum value of IC_*_SPKLEN + 5 for the *_HCNT registers is due to the time required for the DW_apb_i2c to sample SDA during the high period of SCL .
• • The DW_apb_i2c adds one cycle to the programmed *_LCNT value in order to generate the low period of the SCL clock; this is due to the counting logic for SCL low counting to (*_LCNT + 1).
• • The DW_apb_i2c adds IC_*_SPKLEN + 7 cycles to the programmed *_HCNT value in order to generate the high period of the SCL clock, due to the following factors:
  • ◦ The counting logic for SCL high counts to (*_HCNT + 1).
  • ◦ The digital filtering applied to the SCL line incurs a delay of SPKLEN + 2 ic_clk cycles, where SPKLEN is IC_FS_SPKLEN if the component is operating in SS or FS.
  • ◦ Whenever SCL is driven one to zero by the DW_apb_i2c (completing the SCL high time) an internal logic latency of three ic_clk cycles is incurred. Consequently, the minimum SCL low time of which the DW_apb_i2c is capable is nine ic_clk periods (7 + 1 + 1), while the minimum SCL high time is thirteen ic_clk periods (6 + 1 + 3 + 3).

NOTE

The total high time and low time of SCL generated by the DW_apb_i2c master is also influenced by the rise time and fall time of the SCL line, as shown in the illustration and equations in Figure 90 . SCL rise and fall time parameters vary depending on external factors such as:

• • Characteristics of the IO driver
• • Pull-up resistor value
• • Total capacitance on SCL line

These characteristics are beyond the control of the DW_apb_i2c .

Figure 90. Impact of SCL Rise Time and Fall Time on Generated SCL

12.2.14.2. Minimum IC_CLK frequency

This section describes the minimum ic_clk frequencies that the DW_apb_i2c supports for each speed mode, and the associated high and low count values. In slave mode, IC_SDA_HOLD (Thd;dat) and IC_SDA_SETUP (Tsu;dat) need to be programmed to satisfy the I2C protocol timing requirements. The following examples are for the case where IC_FS_SPKLEN is programmed to two.

12.2.14.2.1. Standard Mode (SM), Fast Mode (FM), and Fast Mode Plus (FM+)

This section details how to derive a minimum ic_clk value for standard and fast modes of the DW_apb_i2c . Although the following method shows how to do fast mode calculations, you can also use the same method in order to do calculations for standard mode and fast mode plus.

NOTE

The following computations do not consider the SCL_Rise_time and SCL_Fall_time .

Given conditions and calculations for the minimum DW_apb_i2c ic_clk value in fast mode:

• • Fast mode has data rate of 400 kb/s; implies SCL period of 1/400 kHz = 2.5μs
• • Minimum hcnt value of 14 as a seed value; IC_HCNT_FS = 14
• • Protocol minimum SCL high and low times:
  • ◦ MIN_SCL_LOWtime_FS = 1300 ns
  • ◦ MIN_SCL_HIGHTime_FS = 600 ns

Derived equations:

Combined, the previous equations produce the following:

Solving for IC_LCNT_FS :

The previous equation gives:

These calculations produce IC_LCNT_FS = 16 and IC_HCNT_FS = 14 , giving an ic_clk value of:

Testing these results shows that protocol requirements are satisfied.

Table 1053 lists the minimum ic_clk values for all modes with high and low count values.

Table 1053. ic_clk in Relation to High and Low Counts

• The IC_*_SCL_LCNT and IC_*_SCL_HCNT registers are programmed using the SCL low and high program values in Table 1053 , which are calculated using SCL low count minus one, and SCL high counts minus eight, respectively. The values in Table 1053 are based on IC_SDA_RX_HOLD = 0. The maximum IC_SDA_RX_HOLD value depends on the IC_*CNT registers in Master mode.
• In order to compute the HCNT and LCNT considering RC timings, use the following equations:
  • \( \text{IC\_HCNT\_}^* = [(\text{HCNT} + \text{IC\_}^*\text{SPKLEN} + 7) * \text{ic\_clk}] + \text{SCL\_Fall\_time} \)
  • \( \text{IC\_LCNT\_}^* = [(\text{LCNT} + 1) * \text{ic\_clk}] - \text{SCL\_Fall\_time} + \text{SCL\_Rise\_time} \)

12.2.14.3. Calculating high and low counts

The calculations below show how to calculate SCL high and low counts for each speed mode in the DW_apb_i2c . For the calculations to work, the ic_clk frequencies used must not be less than the minimum ic_clk frequencies specified in Table 1053 .

The default ic_clk period value is set to 100 ns, so default SCL high and low count values are calculated for each speed

mode based on this clock. These values need updating according to the guidelines below.

The equation to calculate the proper number of ic_clk signals required for setting the proper SCL clocks high and low times is as follows:

IC_xCNT = (ROUNDUP(MIN_SCL_xxxtime*OSCFREQ,0))

MIN_SCL_HIGHtime = Minimum High Period

MIN_SCL_HIGHtime = 400ns for 100kb/s,
                  600ns for 400kb/s,
                  260ns for 1000kb/s,

MIN_SCL_LOWtime = Minimum Low Period

MIN_SCL_LOWtime = 470ns for 100kb/s,
                 1300ns for 400kb/s,
                 500ns for 1000kb/s,

OSCFREQ = ic_clk Clock Frequency (Hz).

For example:

OSCFREQ = 100MHz

I2Cmode = fast, 400kb/s

MIN_SCL_HIGHtime = 600ns.

MIN_SCL_LOWtime = 1300ns.

IC_xCNT = (ROUNDUP(MIN_SCL_HIGH_LOWtime*OSCFREQ,0))

IC_HCNT = (ROUNDUP(600ns * 100MHz,0))

IC_HCNTSCL PERIOD = 60

IC_LCNT = (ROUNDUP(1300ns * 100MHz,0))

IC_LCNTSCL PERIOD = 130

Actual MIN_SCL_HIGHtime = 60*(1/100MHz) = 600ns

Actual MIN_SCL_LOWtime = 130*(1/100MHz) = 1300ns

12.2.15. DMA controller interface

The DW_apb_i2c has built-in DMA capability; it has a handshaking interface to the DMA Controller to request and control transfers. The APB bus is used to perform data transfers to and from the DMA. DMA transfers use single accesses, since the data rate is relatively low.

12.2.15.1. Enabling the DMA controller interface

To enable the DMA Controller interface on the DW_apb_i2c , you must write the DMA Control Register ( IC_DMA_CR ). Writing a one into the TDMAE bit field of IC_DMA_CR register enables the DW_apb_i2c transmit handshaking interface. Writing a one into the RDMAE bit field of the IC_DMA_CR register enables the DW_apb_i2c receive handshaking interface.

12.2.15.2. Overview of operation

The DMA Controller is programmed with the number of data items (transfer count) that are to be transmitted or received by DW_apb_i2c .

The transfer is broken into single transfers on the bus, each initiated by a request from the DW_apb_i2c .

For example, where the transfer count programmed into the DMA Controller is four. The DMA transfer consists of a series of four single transactions. If the DW_apb_i2c makes a transmit request to this channel, a single data item is written to the DW_apb_i2c TX FIFO. Similarly, if the DW_apb_i2c makes a receive request to this channel, a single data item is read from the DW_apb_i2c RX FIFO. Four separate requests must be made to this DMA channel before all four data items are written or read.

12.2.15.3. Watermark levels

In DW_apb_i2c the registers for setting watermarks to allow DMA bursts do not need be set to anything other than their reset value. Specifically, IC_DMA_TDLR and IC_DMA_RDLR can be left at reset values of zero. This is because only single transfers are needed due to the low bandwidth of I2C relative to system bandwidth. Because the DMA controller normally has the highest priority on the system bus, transfers complete quickly.

12.2.16. Operation of interrupt registers

Table 1054 lists the operation of the DW_apb_i2c interrupt registers and how they are set and cleared. Some bits are set by hardware and cleared by software, whereas other bits are set and cleared by hardware.

Table 1054. Clearing and Setting of Interrupt Registers

12.2.17. List of registers

The I2C0 and I2C1 registers start at base addresses of 0x40090000 and 0x40098000 respectively (defined as I2C0_BASE and I2C1_BASE in SDK).

You may see references to configuration constants in the I2C register descriptions; these are fixed values, set at hardware design time. A full list of their values can be found in i2c.h in the pico-sdk GitHub repository .

Table 1055. List of I2C registers

I2C: IC_CON Register

Offset: 0x00

Description

I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.

Read/Write Access: - bit 10 is read only - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.

Table 1056. IC_CON Register

I2C: IC_TAR Register

Offset: 0x04

Description

I2C Target Address Register

This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.

Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending

commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.

Table 1057. IC_TAR Register

I2C: IC_SAR Register

Offset: 0x08

Description

I2C Slave Address Register

Table 1058. IC_SAR Register

I2C: IC_DATA_CMD Register

Offset: 0x10

Description

I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.

The size of the register changes as follows:

Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.

Table 1059.
IC_DATA_CMD
Register

I2C: IC_SS_SCL_HCNT Register

Offset: 0x14

Description

Standard Speed I2C Clock SCL High Count Register

Table 1060.
IC_SS_SCL_HCNT
Register

I2C: IC_SS_SCL_LCNT Register

Offset: 0x18

Description

Standard Speed I2C Clock SCL Low Count Register

Table 1061.
IC_SS_SCL_LCNT
Register

I2C: IC_INTR_STAT Register

Offset: 0x2c

Description

I2C Interrupt Status Register

Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.

Table 1064.
IC_INTR_STAT
Register

I2C: IC_INTR_MASK Register

Offset: 0x30

Description

I2C Interrupt Mask Register.

These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.

Table 1065.
IC_INTR_MASK
Register

I2C: IC_RAW_INTR_STAT Register

Offset: 0x34

Description

I2C Raw Interrupt Status Register

Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.

Table 1066.
IC_RAW_INTR_STAT
Register

I2C: IC_RX_TL Register

Offset: 0x38

Description

I2C Receive FIFO Threshold Register

Table 1067. IC_RX_TL Register

I2C: IC_TX_TL Register

Offset: 0x3c

Description

I2C Transmit FIFO Threshold Register

Table 1068. IC_TX_TL Register

I2C: IC_CLR_INTR Register

Offset: 0x40

Description

Clear Combined and Individual Interrupt Register

Table 1069.
IC_CLR_INTR Register

I2C: IC_CLR_RX_UNDER Register

Offset: 0x44

Description

Clear RX_UNDER Interrupt Register

Table 1070.
IC_CLR_RX_UNDER
Register

I2C: IC_CLR_RX_OVER Register

Offset: 0x48

Description

Clear RX_OVER Interrupt Register

Table 1071.
IC_CLR_RX_OVER
Register

I2C: IC_CLR_TX_OVER Register

Offset: 0x4c

Description

Clear TX_OVER Interrupt Register

Table 1072.
IC_CLR_TX_OVER
Register

I2C: IC_CLR_RD_REQ Register

Offset: 0x50

Description

Clear RD_REQ Interrupt Register

Table 1073.
IC_CLR_RD_REQ
Register

I2C: IC_CLR_TX_ABRT Register

Offset: 0x54

Description

Clear TX_ABRT Interrupt Register

Table 1074.
IC_CLR_TX_ABRT
Register

I2C: IC_CLR_RX_DONE Register

Offset: 0x58

Description

Clear RX_DONE Interrupt Register

Table 1075.
IC_CLR_RX_DONE
Register

I2C: IC_CLR_ACTIVITY Register

Offset: 0x5c

Description

Clear ACTIVITY Interrupt Register

Table 1076.
IC_CLR_ACTIVITY
Register

I2C: IC_CLR_STOP_DET Register

Offset: 0x60

Description

Clear STOP_DET Interrupt Register

Table 1077.
IC_CLR_STOP_DET
Register

I2C: IC_CLR_START_DET Register

Offset: 0x64

Description

Clear START_DET Interrupt Register

Table 1078.
IC_CLR_START_DET
Register

I2C: IC_CLR_GEN_CALL Register

Offset: 0x68

Description

Clear GEN_CALL Interrupt Register

Table 1079.
IC_CLR_GEN_CALL
Register

I2C: IC_ENABLE Register

Offset: 0x6c

Description

I2C Enable Register

Table 1080.
IC_ENABLE Register

I2C: IC_STATUS Register

Offset: 0x70

Description

I2C Status Register

This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.

When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0

Table 1081.
IC_STATUS Register

I2C: IC_TXFLR Register

Offset: 0x74

Description

I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.

Table 1082. IC_TXFLR Register

I2C: IC_RXFLR Register

Offset: 0x78

Description

I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.

Table 1083. IC_RXFLR Register

I2C: IC_SDA_HOLD Register

Offset: 0x7c

Description

I2C SDA Hold Time Length Register

The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).

The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in

either master or slave mode.

Writes to this register succeed only when IC_ENABLE[0]=0.

The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.

The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.

Table 1084.
IC_SDA_HOLD
Register

I2C: IC_TX_ABRT_SOURCE Register

Offset: 0x80

Description

I2C Transmit Abort Source Register

This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).

Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.

Table 1085.
IC_TX_ABRT_SOURCE
Register

I2C: IC_SLV_DATA_NACK_ONLY Register

Offset: 0x84

Description

Generate Slave Data NACK Register

The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.

A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.

Table 1086.
IC_SLV_DATA_NACK_ONLY Register

I2C: IC_DMA_CR Register

Offset: 0x88

Description

DMA Control Register

The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.

Table 1087.
IC_DMA_CR Register

I2C: IC_DMA_TDLR Register

Offset: 0x8c

Description

DMA Transmit Data Level Register

Table 1088.
IC_DMA_TDLR
Register

I2C: IC_DMA_RDLR Register

Offset: 0x90

Description

I2C Receive Data Level Register

Table 1089.
IC_DMA_RDLR
Register

I2C: IC_SDA_SETUP Register

Offset: 0x94

This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.

Writes to this register succeed only when IC_ENABLE[0] = 0.

Note: The length of setup time is calculated using \( [(IC\_SDA\_SETUP - 1) * (ic\_clk\_period)] \) , so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.

Table 1090.
IC_SDA_SETUP
Register

Offset: 0x98

The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.

This register is applicable only when the DW_apb_i2c is in slave mode.

Table 1091.
IC_ACK_GENERAL_CALL
Register

Offset: 0x9c

The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.

If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.

If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.

Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.

Table 1092.
IC_ENABLE_STATUS
Register

I2C: IC_FS_SPKLEN Register

Offset: 0xa0

Description

I2C SS, FS or FM+ spike suppression limit

This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.

Table 1093.
IC_FS_SPKLEN
Register

I2C: IC_CLR_RESTART_DET Register

Offset: 0xa8

Description

Clear RESTART_DET Interrupt Register

Table 1094.
IC_CLR_RESTART_DET
Register

I2C: IC_COMP_PARAM_1 Register

Offset: 0xf4

Description

Component Parameter Register 1

Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters

Table 1095.
IC_COMP_PARAM_1
Register

I2C: IC_COMP_VERSION Register

Offset: 0xf8

Description

I2C Component Version Register

Table 1096.
IC_COMP_VERSION
Register

I2C: IC_COMP_TYPE Register

Offset: 0xfc

Description

I2C Component Type Register

Table 1097.
IC_COMP_TYPE
Register

12.3. SPI

Arm Documentation

Excerpted from the ARM PrimeCell Synchronous Serial Port (PL022) Technical Reference Manual . Used with permission.

RP2350 has two identical SPI controllers, both based on an Arm Primecell Synchronous Serial Port (SSP) (PL022) (Revision r1p4). This is distinct from the QSPI memory interface covered in Section 12.14 .

Each controller supports the following features:

• • Master or Slave modes
  • ◦ Motorola SPI-compatible interface
  • ◦ Texas Instruments synchronous serial interface
  • ◦ National Semiconductor Microwire interface
• • 8-location TX and RX FIFOs
• • Interrupt generation to service FIFOs or indicate error conditions
• • Can be driven from DMA
• • Programmable clock rate
• • Programmable data size 4-16 bits

Each controller can be connected to a number of GPIO pins as defined in the Bank 0 GPIO function table, Table 646 ( Section 9.4 ).

The entries in the GPIO function table, such as "SPI0 TX", specify the SPI instance and the SPI signal for that instance which are available on that GPIO. The signals in the table are described as:

SCK

Serial clock. Connects to the SPI peripheral clock signals described as SSPCLKOUT and SSPCLKIN in the following sections. These pins are inputs in slave mode, and outputs in master mode.

TX

Serial data output. Connects to the SPI peripheral SSPTXD (data out) and nSSPOE (output enable) signals described in the following sections. This is always a data output, independent of the bus role. The SPI peripheral controls tristating depending on chip select status.

RX

Serial data input. Connects to the SPI peripheral SSPRXD data input described in the following sections. This is always a data input, independent of the bus role.

CSn

Active-low chip select. Connects to the SPI peripheral signals SSPFSSOUT and SSPFSSIN described in the following sections. These pins are inputs in slave mode, and outputs in master mode.

The SPI uses clk_peri as its reference clock for SPI timing, and is referred to as SSPCLK in the following sections. clk_sys is used as the bus clock, and is referred to as PCLK in the following sections (also see Figure 33 ).

12.3.1. Changes from RP2040

The output enable of the SSPTXD data output (connecting to pins listed as SPI0 TX and SPI1 TX in the GPIO function tables) is controlled by the SPI peripheral nSSP0E signal. The peripheral automatically tristates its output when deselected in slave mode. This makes software control of the output enable unnecessary even when multiple slaves share the data lines.

12.3.2. Overview

The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces.

The PrimeCell SSP performs serial-to-parallel conversion on data received from a peripheral device. The CPU accesses data, control, and status information through the AMBA APB interface. The transmit and receive paths are buffered with internal FIFO memories, enabling up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data transmits on SSPTXD and is received on SSPRXD .

The PrimeCell SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock, SSPCLKOUT , from the input clock, SSPCLK . Bit rates are supported to 2MHz and higher, subject to choice of frequency for SSPCLK , and the maximum bit rate is determined by peripheral devices.

You can use the control registers SSPCR0 and SSPCR1 to program the PrimeCell SSP operating mode, frame format, and size.

The following individually maskable interrupts are generated:

• • SSPTXINTR requests servicing of the transmit buffer
• • SSPRXINTR requests servicing of the receive buffer
• • SSPRORINTR indicates an overrun condition in the receive FIFO
• • SSPRTINTR indicates that a timeout period expired while data was present in the receive FIFO.

A single combined interrupt is asserted if any of the individual interrupts are asserted and unmasked. This interrupt is connected to the processor interrupt controllers in RP2350.

In addition to the above interrupts, a set of DMA signals are provided for interfacing with a DMA controller.

Depending on the operating mode selected, the SSPFSSOUT output operates as:

• • an active-HIGH frame synchronization output for Texas Instruments synchronous serial frame format
• • an active-LOW slave select for SPI and Microwire.

12.3.3. Functional description

Figure 91. PrimeCell SSP block diagram.
For clarity, does not show the test logic.

12.3.3.1. AMBA APB interface

The AMBA APB interface generates read and write decodes for accesses to status and control registers, and transmit and receive FIFO memories.

12.3.3.2. Register block

The register block stores data written, or to be read, across the AMBA APB interface.

12.3.3.3. Clock prescaler

When configured as a master, an internal prescaler, comprising two free-running reloadable serially linked counters, provides the serial output clock SSPCLKOUT .

You can program the clock prescaler, using the SSPCPSR register, to divide SSPCLK by a factor of 2-254 in steps of two. By not utilizing the least significant bit of the SSPCPSR register, division by an odd number is not possible; this ensures that a symmetrical clock with equal mark-space ratio is generated. See SSPCPSR .

The output of the prescaler is divided again by a factor of 1-256, by programming the SSPCR0 control register, to give the final master output clock SSPCLKOUT .

i NOTE

The PCLK and SSPCLK clock inputs in Figure 91 are connected to the clk_sys and clk_peri system-level clock nets on RP2350, respectively. By default, clk_peri attaches directly to the system clock. However, you can detach it to maintain constant SPI frequency if the system clock is varied dynamically. See Figure 33 for an overview of the RP2350 clock architecture.

12.3.3.4. Transmit FIFO

The common transmit (TX) FIFO is a 16-bit wide, 8-location deep memory buffer. CPU data written across the AMBA

APB interface is stored in the buffer until read out by the transmit logic.

When configured as a master or a slave, parallel data is written into the transmit FIFO prior to serial conversion, and transmission to the attached slave or master respectively, through the SSPTXD pin.

12.3.3.5. Receive FIFO

The common receive (RX) FIFO is a 16-bit wide, 8-location deep memory buffer. Received data from the serial interface is stored in the buffer until read out by the CPU across the AMBA APB interface.

When configured as a master or slave, serial data received through the SSPRXD pin is registered prior to parallel loading into the attached slave or master receive FIFO respectively.

12.3.3.6. Transmit and receive logic

When configured as a master, the clock for the attached slaves is derived from a divided-down version of SSPCLK through the previously described prescaler operations. The master transmit logic successively reads a value from its transmit FIFO and performs parallel to serial conversion on it. Then, the serial data stream and frame control signal, synchronized to SSPCLKOUT , outputs through the SSPTXD pin to the attached slaves. The master receive logic performs serial to parallel conversion on the incoming synchronous SSPRXD data stream, extracting and storing values into its receive FIFO for subsequent reading through the APB interface.

When configured as a slave, the SSPCLKIN clock is provided by an attached master and used to time transmission and reception sequences. The slave transmit logic, under control of the master clock, successively:

1. 1. Reads a value from its transmit FIFO.
2. 2. Performs parallel to serial conversion.
3. 3. Outputs the serial data stream and frame control signal through the slave SSPTXD pin.

The slave receive logic performs serial to parallel conversion on the incoming SSPRXD data stream, extracting and storing values into its receive FIFO, for subsequent reading through the APB interface.

12.3.3.7. Interrupt generation logic

The PrimeCell SSP generates four individual maskable, active-HIGH interrupts. A combined interrupt output is generated as an OR function of the individual interrupt requests.

The transmit and receive dynamic data-flow interrupts, SSPTXINTR and SSPRXINTR , are separated from the status interrupts so that data can be read or written in response to the FIFO trigger levels.

12.3.3.8. DMA interface

The PrimeCell SSP provides an interface to connect to a DMA controller, see Section 12.3.4.16 .

12.3.3.9. Synchronizing registers and logic

The PrimeCell SSP supports both asynchronous and synchronous operation of the clocks, PCLK and SSPCLK . Synchronization registers and handshaking logic have been implemented, and are active at all times. Synchronization of control signals is performed on both directions of data flow, that is:

• • from the PCLK to the SSPCLK domain
• • from the SSPCLK to the PCLK domain.

12.3.4. Operation

12.3.4.1. Interface reset

The PrimeCell SSP is reset by the global reset signal, \( \overline{\text{PRESETn}} \) , and a block-specific reset signal, \( \text{nSSPRST} \) . The device reset controller asserts \( \text{nSSPRST} \) asynchronously and negates it synchronously to \( \text{SSPCLK} \) .

12.3.4.2. Configuring the SSP

Following reset, the PrimeCell SSP logic is disabled and must be configured when in this state. It is necessary to program control registers \( \text{SSPCR0} \) and \( \text{SSPCR1} \) to configure the peripheral as a master or slave operating under one of the following protocols:

• • Motorola SPI
• • Texas Instruments SSI
• • National Semiconductor

The bit rate, derived from the external \( \text{SSPCLK} \) , requires the programming of the clock prescale register \( \text{SSPCPSR} \) .

12.3.4.3. Enable PrimeCell SSP operation

You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell SSP is disabled, or permit the transmit FIFO service request to interrupt the CPU. Once enabled, transmission or reception of data begins on the transmit, \( \text{SSPTXD} \) , and receive, \( \text{SSPRXD} \) , pins.

12.3.4.4. Clock ratios

There is a constraint on the ratio of the frequencies of \( \text{PCLK} \) to \( \text{SSPCLK} \) . The frequency of \( \text{SSPCLK} \) must be less than or equal to that of \( \text{PCLK} \) . This ensures that control signals from the \( \text{SSPCLK} \) domain to the \( \text{PCLK} \) domain are guaranteed to get synchronized before one frame duration:

In the slave mode of operation, the \( \text{SSPCLKIN} \) signal from the external master is double-synchronized and then delayed to detect an edge. It takes three \( \text{SSPCLKs} \) to detect an edge on \( \text{SSPCLKIN} \) . \( \text{SSPTXD} \) has less setup time to the falling edge of \( \text{SSPCLKIN} \) on which the master is sampling the line.

The setup and hold times on \( \text{SSPRXD} \) , with reference to \( \text{SSPCLKIN} \) , must be more conservative to ensure that it is at the right value when the actual sampling occurs within the \( \text{SSPMS} \) . To ensure correct device operation, \( \text{SSPCLK} \) must be at least 12 times faster than the maximum expected frequency of \( \text{SSPCLKIN} \) .

The frequency selected for \( \text{SSPCLK} \) must accommodate the desired range of bit clock rates. The ratio of minimum \( \text{SSPCLK} \) frequency to \( \text{SSPCLKOUT} \) maximum frequency in the case of the slave mode is 12, and for the master mode, it is two.

For example, at the maximum \( \text{SSPCLK} \) ( \( \text{clk\_peri} \) ) frequency on RP2350 of 150MHz, the maximum peak bit rate in master mode is 70.5Mb/s. This is achieved with the \( \text{SSPCPSR} \) register programmed with a value of 2, and the \( \text{SCR}[7:0] \) field in the \( \text{SSPCR0} \) register programmed with a value of 0.

In slave mode, the same maximum \( \text{SSPCLK} \) frequency of 150MHz can achieve a peak bit rate of \( 150 / 12 = 12.5\text{Mb/s} \) . The \( \text{SSPCPSR} \) register can be programmed with a value of 12, and the \( \text{SCR}[7:0] \) field in the \( \text{SSPCR0} \) register can be programmed with a value of 0. Similarly, the ratio of \( \text{SSPCLK} \) maximum frequency to \( \text{SSPCLKOUT} \) minimum frequency is \( 254 \times 256 \) .

The minimum frequency of \( \text{SSPCLK} \) is governed by the following inequalities, both of which must be satisfied:

\( F_{SSPCLK}(min) \geq 12 \times F_{SSPCLKIN}(max) \) , for slave mode.

The maximum frequency of SSPCLK is governed by the following inequalities, both of which must be satisfied:

\( F_{SSPCLK}(max) \leq 254 \times 256 \times F_{SSPCLKOUT}(min) \) , for master mode

\( F_{SSPCLK}(max) \leq 254 \times 256 \times F_{SSPCLKIN}(min) \) , for slave mode.

12.3.4.5. Programming the SSPCR0 control register

The SSPCR0 register is used to:

• • program the serial clock rate
• • select one of the three protocols
• • select the data word size, where applicable.

The Serial Clock Rate (SCR) value, in conjunction with the SSPCPSR clock prescale divisor value, CPSDVSR , is used to derive the PrimeCell SSP transmit and receive bit rate from the external SSPCLK .

The frame format is programmed through the FRF bits, and the data word size through the DSS bits.

Bit phase and polarity, applicable to Motorola SPI format only, are programmed through the SPH and SP0 bits.

12.3.4.6. Programming the SSPCR1 control register

The SSPCR1 register is used to:

• • select master or slave mode
• • enable a loop back test feature
• • enable the PrimeCell SSP peripheral.

To configure the PrimeCell SSP as a master, clear the SSPCR1 register master or slave selection bit, MS, to 0. This is the default value on reset.

Setting the SSPCR1 register MS bit to 1 configures the PrimeCell SSP as a slave. When configured as a slave, use the SSPCR1 slave mode SSPTXD output disable bit ( SOD ) to enable or disable of the PrimeCell SSP SSPTXD signal. You can use this in some multi-slave environments where masters might parallel broadcast.

To enable the PrimeCell SSP, set the Synchronous Serial Port Enable ( SSE ) bit to 1.

12.3.4.6.1. Bit rate generation

The serial bit rate is derived by dividing down the input clock, SSPCLK . The clock is first divided by an even prescale value CPSDVSR in the range 2-254, and is programmed in SSPCPSR . The clock is divided again by a value in the range 1-256, that is \( 1 + SCR \) , where SCR is the value programmed in SSPCR0 .

The following equation defines the frequency of the output signal bit clock, SSPCLKOUT :

For example, if SSPCLK is 125MHz, and CPSDVSR = 2, then SSPCLKOUT has a frequency range from 244kHz - 62.5MHz.

12.3.4.7. Frame format

Each data frame is between 4-16 bits long, depending on the size of data programmed, and is transmitted starting with the MSB. You can select the following basic frame types:

• • Texas Instruments synchronous serial
• • Motorola SPI
• • National Semiconductor Microwire.

For all formats, the serial clock, SSPCLKOUT , is held inactive while the PrimeCell SSP is idle, and transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSPCLKOUT is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period.

For Motorola SPI and National Semiconductor Microwire frame formats, the serial frame, SSPFSSOUT , pin is active-LOW, and is asserted, pulled-down, during the entire transmission of the frame.

For Texas Instruments synchronous serial frame format, the SSPFSSOUT pin is pulsed for one serial clock period, starting at its rising edge, prior to the transmission of each frame. For this frame format, both the PrimeCell SSP and the off-chip slave device drive their output data on the rising edge of SSPCLKOUT , and latch data from the other device on the falling edge.

Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor Microwire format uses a special master-slave messaging technique that operates at half-duplex. In this mode, when a frame begins, an 8-bit control message is transmitted to the off-chip slave. During this transmit, the SSS receives no incoming data. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. The returned data can be 4-16 bits in length, making the total frame length in the range 13-25 bits.

12.3.4.8. Texas Instruments synchronous serial frame format

Figure 92 shows the Texas Instruments synchronous serial frame format for a single transmitted frame.

Figure 92. Texas Instruments synchronous serial frame format, single transfer

In this mode, SSPCLKOUT and SSPFSSOUT are forced LOW, and the transmit data line, SSPTXD is tristated whenever the PrimeCell SSP is idle. When the bottom entry of the transmit FIFO contains data, SSPFSSOUT is pulsed HIGH for one SSPCLKOUT period. The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the transmit logic. On the next rising edge of SSPCLKOUT , the MSB of the 4-bit to 16-bit data frame is shifted out on the SSPTXD pin. In a similar way, the MSB of the received data is shifted onto the SSPRXD pin by the off-chip serial slave device.

Both the PrimeCell SSP and the off-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SSPCLKOUT . The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of CLK after the LSB has been latched.

Figure 93 shows the Texas Instruments synchronous serial frame format when back-to-back frames are transmitted.

Figure 93. Texas Instruments synchronous serial frame format, continuous transfer

12.3.4.9. Motorola SPI frame format

The Motorola SPI interface is a four-wire interface where the SSPFSSOUT signal behaves as a slave select. The main feature of the Motorola SPI format is that you can program the inactive state and phase of the SSPCLKOUT signal using the SP0 and SPH bits of the SSPSCR0 control register.

12.3.4.9.1. SP0, clock polarity

When the SP0 clock polarity control bit is LOW, it produces a steady state LOW value on the SSPCLKOUT pin. If the SP0 clock polarity control bit is HIGH, a steady state HIGH value is placed on the SSPCLKOUT pin when data is not being transferred.

12.3.4.9.2. SPH, clock phase

The SPH control bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.

When the SPH phase control bit is LOW, data is captured on the first clock edge transition.

When the SPH clock phase control bit is HIGH, data is captured on the second clock edge transition.

12.3.4.10. Motorola SPI format with SP0=0, SPH=0

Figure 94 and Figure 95 shows a continuous transmission signal sequence for Motorola SPI frame format with SP0=0 , SPH=0 . Figure 94 shows a single transmission signal sequence for Motorola SPI frame format with SP0=0 , SPH=0 .

Figure 94. Motorola SPI frame format, single transfer, with SP0=0 and SPH=0

Figure 95 shows a continuous transmission signal sequence for Motorola SPI frame format with SP0=0 , SPH=0 .

Figure 95. Motorola SPI frame format, single transfer, with SP0=0 and SPH=0

In this configuration, during idle periods:

• • the SSPCLKOUT signal is forced LOW
• • the SSPFSSOUT signal is forced HIGH
• • the transmit data line SSPTXD is arbitrarily forced LOW
• • the nSSPOE pad enable signal is forced HIGH (this is not connected to the pad in RP2350)
• • when the PrimeCell SSP is configured as a master, the nSSPCTL0E line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable
• • when the PrimeCell SSP is configured as a slave, the nSSPCTL0E line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable

If the PrimeCell SSP is enable, and there is valid data within the transmit FIFO, the start of transmission is signified by the SSPFSSOUT master signal being driven LOW. This causes slave data to be enabled onto the SSPRXD input line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad.

One-half SSPCLKOUT period later, valid master data is transferred to the SSPTXD pin. Now that both the master and slave data have been set, the SSPCLKOUT master clock pin goes HIGH after one additional half SSPCLKOUT period.

The data is now captured on the rising and propagated on the falling edges of the SSPCLKOUT signal.

In the case of a single word transmission, after all bits of the data word have been transferred, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.

However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal pulse HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured.

12.3.4.11. Motorola SPI format with SPO=0, SPH=1

Figure 96 shows the transfer signal sequence for Motorola SPI format with SPO=0 , SPH=1 , and it covers both single and continuous transfers.

Figure 96. Motorola SPI frame format with SPO=0 and SPH=1, single and continuous transfers

In this configuration, during idle periods:

• the SSPCLKOUT signal is forced LOW
• The SSPFSSOUT signal is forced HIGH
• the transmit data line SSPTXD is arbitrarily forced LOW
• the nSSPOE pad enable signal is forced HIGH (not connected to the pad in RP2350)
• when the PrimeCell SSP is configured as a master, the nSSPCTL0E line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable
• when the PrimeCell SSP is configured as a slave, the nSSPCTL0E line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission is signified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad. After an additional one half SSPCLKOUT period, both master and slave valid data is enabled onto their respective transmission lines. At the same time, the SSPCLKOUT is enabled with a rising edge transition.

Data is then captured on the falling edges and propagated on the rising edges of the SSPCLKOUT signal.

In the case of a single word transfer, after all bits have been transferred, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured. For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer.

12.3.4.12. Motorola SPI format with SPO=1, SPH=0

Figure 97 and Figure 98 show single and continuous transmission signal sequences for Motorola SPI format with SPO=1, SPH=0.

Figure 97 shows a single transmission signal sequence for Motorola SPI format with SPO=1, SPH=0.

Figure 97. Motorola SPI frame format, single transfer, with SPO=1 and SPH=0

Figure 98 shows a continuous transmission signal sequence for Motorola SPI format with SPO=1, SPH=0.

i NOTE

In Figure 97, Q is an undefined signal.

Figure 98. Motorola SPI frame format, continuous transfer, with SPO=1 and SPH=0

In this configuration, during idle periods:

• • the SSPCLKOUT signal is forced HIGH
• • the SSPFSSOUT signal is forced HIGH
• • the transmit data line SSPTXD is arbitrarily forced LOW
• • the nSSPOE pad enable signal is forced HIGH (not connected to the pad in RP2350)
• • when the PrimeCell SSP is configured as a master, the nSSPCTL0E line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable
• • when the PrimeCell SSP is configured as a slave, the nSSPCTL0E line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission is signified by the SSPFSSOUT master signal being driven LOW, and this causes slave data to be immediately transferred onto the SSPRXD line of the master. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad.

One half period later, valid master data is transferred to the SSPTXD line. Now that both the master and slave data have been set, the SSPCLKOUT master clock pin becomes LOW after one additional half SSPCLKOUT period. This means that data is captured on the falling edges and be propagated on the rising edges of the SSPCLKOUT signal.

In the case of a single word transmission, after all bits of the data word are transferred, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.

However, in the case of continuous back-to-back transmissions, the SSPFSSOUT signal must be pulsed HIGH between each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and does not permit it to be altered if the SPH bit is logic zero. Therefore, the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after the last bit has been captured.

12.3.4.13. Motorola SPI format with SPO=1, SPH=1

Figure 99 shows the transfer signal sequence for Motorola SPI format with SPO=1, SPH=1, and it covers both single and continuous transfers.

Figure 99. Motorola SPI frame format with SPO=1 and SPH=1, single and continuous transfers

NOTE

In Figure 99, Q is an undefined signal.

In this configuration, during idle periods:

• • the SSPCLKOUT signal is forced HIGH
• • the SSPFSSOUT signal is forced HIGH
• • the transmit data line SSPTXD is arbitrarily forced LOW
• • the nSSPOE pad enable signal is forced HIGH (not connected to the pad in RP2350)
• • when the PrimeCell SSP is configured as a master, the nSSPCTL0E line is driven LOW, enabling the SSPCLKOUT pad, active-LOW enable
• • when the PrimeCell SSP is configured as a slave, the nSSPCTL0E line is driven HIGH, disabling the SSPCLKOUT pad, active-LOW enable.

If the PrimeCell SSP is enabled, and there is valid data within the transmit FIFO, the start of transmission is signified by the SSPFSSOUT master signal being driven LOW. The nSSPOE line is driven LOW, enabling the master SSPTXD output pad. After an additional one half SSPCLKOUT period, both master and slave data are enabled onto their respective transmission lines. At the same time, the SSPCLKOUT is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSPCLKOUT signal.

After all bits have been transferred, in the case of a single word transmission, the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured.

For continuous back-to-back transmissions, the SSPFSSOUT pin remains in its active-LOW state, until the final bit of the last word has been captured, and then returns to its idle state as the previous section describes.

For continuous back-to-back transfers, the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer.

12.3.4.14. National Semiconductor Microwire frame format

Figure 100 shows the National Semiconductor Microwire frame format for a single frame. Figure 101 shows the same format when back to back frames are transmitted.

Figure 100. Microwire frame format, single transfer

Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the PrimeCell SSP to the off-chip slave device. During this transmission, the PrimeCell SSP receives no incoming data. After the message has been sent, the off-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. The returned data is 4 to 16 bits in length, making the total frame length in the range 13-25 bits.

In this configuration, during idle periods:

• • SSPCLKOUT is forced LOW
• • SSPFSSOUT is forced HIGH
• • the transmit data line, SSPTXD , is arbitrarily forced LOW
• • the nSSPOE pad enable signal is forced HIGH (not connected to the pad in RP2350)

A transmission is triggered by writing a control byte to the transmit FIFO. The falling edge of SSPFSSOUT causes the value contained in the bottom entry of the transmit FIFO to be transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control frame to be shifted out onto the SSPTXD pin. SSPFSSOUT remains LOW for the duration of the frame transmission. The SSPRXD pin remains tristated during this transmission.

The off-chip serial slave device latches each control bit into its serial shifter on the rising edge of each SSPCLKOUT . After the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the PrimeCell SSP. Each bit is driven onto SSPRXD line on the falling edge of SSPCLKOUT . The PrimeCell SSP in turn latches each bit on the rising edge of SSPCLKOUT . At the end of the frame, for single transfers, the SSPFSSOUT signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.

NOTE

The off-chip slave device can tristate the receive line either on the falling edge of SSPCLKOUT after the LSB has been latched by the receive shifter, or when the SSPFSSOUT pin goes HIGH.

For continuous transfers, data transmission begins and ends in the same manner as a single transfer. However, the SSPFSSOUT line is continuously asserted, held LOW, and transmission of data occurs back-to-back. The control byte of the next frame follows directly after the LSB of the received data from the current frame. Each of the received values is transferred from the receive shifter on the falling edge SSPCLKOUT , after the LSB of the frame has been latched into the PrimeCell SSP.

Figure 101 shows the National Semiconductor Microwire frame format when back-to-back frames are transmitted.

Figure 101. Microwire frame format, continuous transfers

In Microwire mode, the PrimeCell SSP slave samples the first bit of receive data on the rising edge of SSPCLKIN after SSPFSSIN has gone LOW. Masters that drive a free-running SSPCLKIN must ensure that the SSPFSSIN signal has sufficient setup and hold margins with respect to the rising edge of SSPCLKIN .

Figure 102 shows these setup and hold time requirements.

Figure 104. PrimeCell SSP master coupled to an SPI slave

Figure 105 shows a Motorola SPI configured as a master and interfaced to an instance of a PrimeCell SSP (PL022) configured as a slave. In this case, the slave Select Signal ( \( \overline{SS} \) ) is permanently tied HIGH to configure it as a master. The master can broadcast to the slave through the master SPI MOSI line and in response, the slave drives its nSSPOE signal LOW. This enables its SSPTXD data onto the MISO line of the master.

Figure 105. SPI master coupled to a PrimeCell SSP slave

12.3.4.16. PrimeCell DMA interface

The PrimeCell SSP provides an interface to connect to the DMA controller. The PrimeCell SSP DMA control register, SSPDMACR controls the DMA operation of the PrimeCell SSP.

The DMA interface includes the following signals, for receive:

SSPRXDMASREQ

Single-character DMA transfer request, asserted by the SSP. This signal is asserted when the receive FIFO contains at least one character.

SSPRXDMABREQ

Burst DMA transfer request, asserted by the SSP. This signal is asserted when the receive FIFO contains four or more characters.

SSPRXDACLK

DMA request clear, asserted by the DMA controller to clear the receive request signals. If DMA burst transfer is requested, the clear signal is asserted during the transfer of the last data in the burst.

The DMA interface includes the following signals, for transmit:

SSPTXDMASREQ

Single-character DMA transfer request, asserted by the SSP. This signal is asserted when there is at least one empty location in the transmit FIFO.

SSPTXDMABREQ

Burst DMA transfer request, asserted by the SSP. This signal is asserted when the transmit FIFO contains four characters or fewer.

SSPTXDMACLR

DMA request clear, asserted by the DMA controller, to clear the transmit request signals. If a DMA burst transfer is requested, the clear signal is asserted during the transfer of the last data in the burst.

The burst transfer and single transfer request signals are not mutually exclusive. They can both be asserted at the same time. For example, when there is more data than the watermark level of four in the receive FIFO, the burst transfer request, and the single transfer request, are asserted. When the amount of data left in the receive FIFO is less than the watermark level, the single request only is asserted. This is useful for situations where the number of characters left to be received in the stream is less than a burst.

For example, if 19 characters must be received, the DMA controller then transfers four bursts of four characters, and three single transfers to complete the stream.

NOTE

For the remaining three characters, the PrimeCell SSP does not assert the burst request.

Each request signal remains asserted until the relevant DMA clear signal is asserted. After the request clear signal is de-asserted, a request signal can become active again, depending on the conditions that previous sections describe. All request signals are de-asserted if the PrimeCell SSP is disabled, or the DMA enable signal is cleared.

Table 1098 shows the trigger points for DMABREQ, for both the transmit and receive FIFOs.

Table 1098. DMA trigger points for the transmit and receive FIFOs

Figure 106 shows the timing diagram for both a single transfer request, and a burst transfer request, with the appropriate DMA clear signal. The signals are all synchronous to PCLK.

Figure 106. DMA transfer waveforms

12.3.5. List of registers

The SPI0 and SPI1 registers start at base addresses of 0x40080000 and 0x40088000 respectively (defined as SPI0_BASE and SPI1_BASE in SDK).

Table 1099. List of SPI registers

SPI: SSPCR0 Register

Offset: 0x000

Description

Control register 0, SSPCR0 on page 3-4

Table 1100. SSPCR0 Register

SPI: SSPCR1 Register

Offset: 0x004

Description

Control register 1, SSPCR1 on page 3-5

Table 1101. SSPCR1 Register

SPI: SSPDR Register

Offset: 0x008

Description

Data register, SSPDR on page 3-6

Table 1102. SSPDR Register

SPI: SSPSR Register

Offset: 0x00c

Description

Status register, SSPSR on page 3-7

Table 1103. SSPSR Register

SPI: SSPCPSR Register

Offset: 0x010

Description

Clock prescale register, SSPCPSR on page 3-8

Table 1104. SSPCPSR Register

SPI: SSPIMSC Register

Offset: 0x014

Description

Interrupt mask set or clear register, SSPIMSC on page 3-9

Table 1105. SSPIMSC Register

SPI: SSPRIS Register

Offset: 0x018

Description

Raw interrupt status register, SSPRIS on page 3-10

Table 1106. SSPRIS Register

SPI: SSPMIS Register

Offset: 0x01c

Description

Masked interrupt status register, SSPMIS on page 3-11

Table 1107. SSPMIS Register

SPI: SSPICR Register

Offset: 0x020

Description

Interrupt clear register, SSPICR on page 3-11

Table 1108. SSPICR Register

SPI: SSPDMACR Register

Offset: 0x024

Description

DMA control register, SSPDMACR on page 3-12

Table 1109. SSPDMACR Register